Abstract: Various embodiments herein relate to methods and systems for backscatter communication using pre-defined templates. In accordance with at least one embodiment, there is provided a backscattering communication system, comprising a transmitting unit, a backscattering tag, and a receiving unit. The transmitting unit is configured to transmit a signal comprising a transmitted frame including a pre-defined data payload. The backscattering tag is configured to: receive, from the transmitting unit, the signal comprising the transmitted frame; encode tag data over the pre-defined data payload to generate a modified data payload; and transmit a backscattered signal comprising a backscattered frame including the modified data payload.

Abstract: This invention is an apparatus that, connected to a computer program, controls the process of filling of pills in trays for medicine dispensers or pillboxes with multiple chambers. The apparatus is characterized by applying a control scanner and a precision weight for precise dispensing of the pills and by gate templates to guide the pills to selected chambers in the target pillboxes. Target chambers are automatically selected according to the pre-determined ingestion time. The pills will remain in the gate-template until the operator has conducted a visual inspection and/or performed a semi-automatic camera control to verify that the pills are properly distributed in the openings of the gate template. After the verification process, the pills are released into medication tray, by means of a mechanical device with double barrier plates, which are activated by a specialized release mechanism.

Abstract: A cell library is automatically designed. An emphasis of a design methodology is on automatic determination of the desired or needed cell sizes and variants. This method exploits different variants on drive strengths, P/N ratios, topology variants, internal buffering, and so forth. The method allows generating libraries that are more suitable for efficient timing closure.

Abstract: Methods are used to enrich a cell library in such a way to provide a nearly continuous choice of cells to implement a circuit design. The emphasis of the design method is on automatic determination of the needed cell sizes and variants. The method exploits different variants on drive strengths, P/N ratios, topology variants, internal buffering, and so forth. The method allows enriching libraries to become more suitable for efficient timing closure. The method also offers means to adapt the preexisting cells to fit the final distribution, minimizing the number of new cells to be created.

Abstract: A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library.

Abstract: A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library.

Abstract: A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library.

Abstract: A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library.

Abstract: A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library.

Abstract: A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library.

Abstract: A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library.

Abstract: A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library.

Abstract: A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library.

Abstract: A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library.

Abstract: A switching unit and a method for operating the same as well as a device for use in the switching unit, where the switching unit comprises a ring-shaped bus for transporting the data packets and a daisy-chain type bus for transporting controlling device information for use in a later switching routing. The two busses are driven synchronously. This systolic nature of the busses ensures optimal bandwidth of the switching.