Patents by Inventor Ole H. Moller

Ole H. Moller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6292845
    Abstract: An instruction fetching unit is described for loading instructions from a memory processed by a data processing device. The instruction code can be of at least two different lengths, and each instruction contains at least a single bit indicating said instruction sizes. An instruction buffer coupled with an instruction size evaluation unit for determining the instruction size upon said at least single bit of said instruction is provided.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: September 18, 2001
    Assignee: Infineon Technologies North America Corp.
    Inventors: Rod G. Fleck, Bruce Holmer, Ole H. Møller, Roger D. Arnold, Balraj Singh
  • Patent number: 6076159
    Abstract: A data processor is disclosed which comprises a first pipeline for decoding and executing data instructions, a second pipeline for decoding and executing address instructions, a unit for issuing multiple instructions to the pipelines, a first set of registers being coupled with the first pipeline, and a second set of registers being coupled with the second pipeline, wherein first and second pipeline process data in parallel.
    Type: Grant
    Filed: September 12, 1997
    Date of Patent: June 13, 2000
    Assignee: Siemens Aktiengesellschaft
    Inventors: Rod G. Fleck, Ole H. Moller, Gigy Baror
  • Patent number: 4926323
    Abstract: A streamlined instruction processor processes data in response to a program composed of prespecified instructions in pipeline cycles. The processor comprises an instruction fetch unit, including an instruction interface adapted for connection to an instruction memory and for fetching instructions from the instruction memory. The instruction fetch unit includes an instruction prefetch buffer coupled to the instruction interface for buffering a sequence of instructions supplied to the instruction interface. A branch target cache is coupled with the prefetch buffer for storing sets of instructions retrieved from a corresponding set of locations in the instruction memory, having sequential instruction addresses. The first instruction in each such set is a branch target instruction in the program.In addition, an execution unit including a data interface adapted for connection to the data memory, executes the instructions in pipeline cycles.
    Type: Grant
    Filed: March 3, 1988
    Date of Patent: May 15, 1990
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gigy Baror, Brian W. Case, Rod G. Fleck, Philip M. Freidin, Smeeta Gupta, William M. Johnson, Cheng-Gang Kong, Ole H. Moller, Timothy A. Olson, David I. Sorensen
  • Patent number: 4868735
    Abstract: A one-chip, integrated-circuit, microprogram sequence controller for use in a microprogrammed system having a data processing unit and a microprogram memory, that controls the order and execution of microinstructions within the microprogram memory. The controller is provided with two 16-bit microinstruction address input busses and a 16-bit output bus on which microinstruction addresses are issued to the microprogram memory. One of the input busses and the output busses are bidirectional providing access to various on-chip parameters such as the contents of the top of an on-chip stack memory or the value of an on-chip stack pointer. An on-chip comparator permits trapping of a microinstruction at a specified address or gathering of run-time statistics. A structured, 64-element instruction set is provided which includes sixteen special-function continue instructions which perform additional operations without imposing added time requirements.
    Type: Grant
    Filed: February 3, 1989
    Date of Patent: September 19, 1989
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ole H. Moller, Sanjay Iyer, Paul P. L. Chu
  • Patent number: 4760374
    Abstract: A bounds checker consisting of a pair of comparators that each compare a 16-bit number with a lower and an upper limit stored in registers. The device is preferably constructed as a single integrated circuit chip employing emitter coupled logic (ECL) circuitry and can be made externally compatible with either transistor transistor logic (TTL) circuitry or ECL circuitry. The device can be cascaded to operate on extended-precision numbers and has a pin which can be used to select comparison of numbers either as signed two's complement numbers or as unsigned numbers. No added gate delay is imposed by the device's ability to operate either type of number.
    Type: Grant
    Filed: November 29, 1984
    Date of Patent: July 26, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Ole H. Moller
  • Patent number: 4719565
    Abstract: A single-chip microprogram sequence controller can be selectively operated in either an interrupt mode or a trapped mode. In the interrupt mode, the miroprogram sequencer allows the currently-executing microinstruction to finish execution before beginning the interrupt routine which services the asynchronous event which requested the interruption of the presently-executing microinstruction stream. In the trap mode, the sequencer aborts the currently-executing microinstruction to avoid an irreversible error which would result if the microinstruction were to finish execution before beginning the routine which services the event which requested trapping of the presently-executing microinstruction.
    Type: Grant
    Filed: November 1, 1984
    Date of Patent: January 12, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Ole H. Moller
  • Patent number: 4610004
    Abstract: A two read-port, two write-port register file on a single integrated circuit chip provides dual read/write access via either an "A"-side or a "B"-side of a single array of addressable registers. Separate on-chip "A"-side and "B"-side multiplexers permit reading or writing of an independently addressed register according to the phase of the "A"-side or "B"-side clock. Writing can be selectively effected to either a high-order and/or a low-order byte within the addressed register. Unidirectional busses connect each register to each of the four ports. The register can be expanded to provide a four read-port, two write-port register file such as is required for the parallel computation of addresses and data.
    Type: Grant
    Filed: October 10, 1984
    Date of Patent: September 2, 1986
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ole H. Moller, Paul Po Loi Chu