Abstract: An ultrasound imaging system (100) includes at least first and second arrays (108) of transducer elements, which are angularly offset from each other in a same plane. Transmit circuitry (112) excites the first and second arrays to concurrently transmit over a plurality of angles. Receive circuitry (114) controls the first and second arrays to concurrently receive echo signals over the plurality of angles. An echo processor (116) processes the received signals, producing a first data stream for the first array and a second data stream for the second array. The first and second data streams include digitized representations of the received echo signals. A sample matcher (118) compares samples of the first and second data streams and determines a cross-correlation there between. A correlation factor generator (120) that generates a correlation factor signal based on the determined cross-correlation.

Abstract: An ultrasound imaging system (100) includes at least first and second arrays (108) of transducer elements, which are angularly offset from each other in a same plane. Transmit circuitry (112) excites the first and second arrays to concurrently transmit over a plurality of angles. Receive circuitry (114) controls the first and second arrays to concurrently receive echo signals over the plurality of angles. An echo processor (116) processes the received signals, producing a first data stream for the first array and a second data stream for the second array. The first and second data streams include digitized representations of the received echo signals. A sample matcher (118) compares samples of the first and second data streams and determines a cross-correlation there between. A correlation factor generator (120) that generates a correlation factor signal based on the determined cross-correlation.

Abstract: An ultrasound imaging system (100) includes at least first and second arrays (108) of transducer elements, which are angularly offset from each other in a same plane. Transmit circuitry (112) excites the first and second arrays to concurrently transmit over a plurality of angles. Receive circuitry (114) controls the first and second arrays to concurrently receive echo signals over the plurality of angles. An echo processor (116) processes the received signals, producing a first data stream for the first array and a second data stream for the second array. The first and second data streams include digitized representations of the received echo signals. A sample matcher (118) compares samples of the first and second data streams and determines a cross-correlation there between. A correlation factor generator (120) that generates a correlation factor signal based on the determined cross-correlation.

Abstract: Microphone array for achieving a substantially frequency-independent directivity using a plurality of microphones disposed along a rectilinear array. The rectilinear array is at least as long as the wavelength of the lowest frequency, where a useful directivity is desired. The rectilinear array has a first end and a second end. The microphones close to the first end are intended for the highest frequencies and the microphones close to the second end are intended for the lowest frequencies. The mutual spacing of the microphones is frequency-dependent. The signals from the individual microphones are band-pass filtered, the passbands and cut-off frequencies of the individual band-pass filters being adapted to the frequency band the individual microphones are intended for.

Abstract: Microphone array for achieving a substantially frequency-independent directivity using a plurality of microphones disposed along a rectilinear array. The rectilinear array is at least as long as the wavelength of the lowest frequency, where a useful directivity is desired. The rectilinear array has a first end and a second end. The microphones close to the first end are intended for the highest frequencies and the microphones close to the second end are intended for the lowest frequencies. The mutual spacing of the microphones is frequency-dependent. The signals from the individual microphones are band-pass filtered, the passbands and cut-off frequencies of the individual band-pass filters being adapted to the frequency band the individual microphones are intended for.

Abstract: The apparatus for examining an object by means of ultrasound has an emitting transducer and a receiving transducer with a plurality of transducer elements. Electrical signals from the receiving transducer elements are selectively connected to input taps of a single delay line for individually delaying the electrical signals to compensate for their different distances from points under investigation in the object. For each point in the object a first received echo signal is connected to a first input tap giving a first delay, and subsequently received echo signals are connected to input taps being selected so that the subsequent electrical signals are output on the output tap substantially simultaneously with the electrical signal representing said first received echo. The receiving transducer is thereby adjusted currently during the reception of each scan line to perfectly adapt its focus at each instant in time and with an exceptionally high degree of accuracy.

Abstract: A high speed register file for use by an instruction processor suitable for reduced instruction-set computers (RISCs) is disclosed which is preferably used with an efficient register allocation method. The register file facilitates the passing of parameters between procedures by dynamically providing overlapping registers which are accessible to both procedures. Each procedure also has a set of "local" registers assigned to it which are inaccessible from other procedures. The register file is divided into a number of blocks and a protection register stores a word which proscribes access by a particular procedure or task to certain blocks. In this manner, an instruction processor using the register file can operate on multiple tasks maintaining the integrity of each from undesired changes occuring in the others.

Abstract: An instruction processor suitable for use in a reduced instruction-set computer employs an instruction pipeline which performs conditional branching in a single processor cycle. The processor treats a branch condition as a normal instruction operand rather than a special case within a separate condition code register. The condition bit and the branch target address determine which instruction is to be fetched, the branch not taking effect until the next-following instruction is executed. In this manner, no replacement of the instruction which physically follows the branch instruction in the pipeline need be made, and the branch occurs within the single cycle of the pipeline allocated to it. A simple circuit implements this delayed-branch method. A computer incorporating the processor readily executes special-handling techniques for calls on subroutine, interrupts and traps.

Abstract: A simple architecture to implement a mechanism for performing data references to storage in parallel with instruction execution. The architecture is particularly suited to reduced instruction-set computers (RISCs) and employs a channel address register to store the main memory load or store address, a channel data register which temporarily stores the data from a store operation and, a channel control register which contains control information including the number of the register loaded within the file, in the case of a load operation. This number is used to detect instruction dependency of the data to be loaded. Logic circuitry suspends further instruction processing if the data required from a load is not yet available. A data-in register is used to store load data until an instruction execution cycle is available for writing it back to the register file. Logic circuitry detects storage of data prior to its writing back, so as to effectively replace the register file location.