Patents by Inventor Oleg G. Gluschenkov
Oleg G. Gluschenkov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8633071Abstract: A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.Type: GrantFiled: October 21, 2011Date of Patent: January 21, 2014Assignee: International Business Machines CorporationInventors: Duresti Chidambarrao, Omer H. Dokumaci, Oleg G. Gluschenkov
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Patent number: 8232153Abstract: A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.Type: GrantFiled: June 4, 2007Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Omer H. Dokumaci, Oleg G. Gluschenkov
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Publication number: 20120052653Abstract: A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.Type: ApplicationFiled: October 21, 2011Publication date: March 1, 2012Applicant: International Business Machines CorporationInventors: Duresetl CHIDAMBARRAO, Omer H. Dokumaci, Oleg G. Gluschenkov
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Patent number: 8119472Abstract: A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.Type: GrantFiled: June 4, 2007Date of Patent: February 21, 2012Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Omer H. Dokumaci, Oleg G. Gluschenkov
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Patent number: 8067805Abstract: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.Type: GrantFiled: June 4, 2008Date of Patent: November 29, 2011Assignee: International Business Machines CorporationInventors: Huajie Chen, Omer H. Dokumaci, Oleg G. Gluschenkov, Werner A. Rausch
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Patent number: 8013392Abstract: Semiconductor structure formed on a substrate and process of forming the semiconductor. The semiconductor includes a plurality of field effect transistors having a first portion of field effect transistors (FETS) and a second portion of field effect transistors. A first stress layer has a first thickness and is configured to impart a first determined stress to the first portion of the plurality of field effect transistors. A second stress layer has a second thickness and is configured to impart a second determined stress to the second portion of the plurality of field effect transistors.Type: GrantFiled: September 28, 2007Date of Patent: September 6, 2011Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Oleg G. Gluschenkov, Huilong Zhu
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Patent number: 7847358Abstract: A semiconductor structure formed on a substrate and process for preventing oxidation induced stress in a determined portion of the substrate. The structure includes an n-FET device and a p-FET device, and a shallow trench isolation having at least one overhang is selectively configured to prevent oxidation induced stress in a determined portion of the substrate. The at least one overhang is selectively configured to prevent oxidation induced stress in at least one of a direction parallel to and a direction transverse to a direction of a current flow. For the n-FET device, the at least one overhang is selectively arranged in directions of and transverse to a current flow, and for the p-FET device, the at least one overhang is arranged transverse to the current flow to prevent performance degradation from compressive stresses.Type: GrantFiled: August 4, 2006Date of Patent: December 7, 2010Assignee: International Business Machines CorporationInventors: Bruce B Doris, Oleg G Gluschenkov
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Patent number: 7816237Abstract: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.Type: GrantFiled: June 4, 2008Date of Patent: October 19, 2010Assignee: International Business Machines CorporationInventors: Huajie Chen, Omer H. Dokumaci, Oleg G. Gluschenkov, Werner A. Rausch
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Patent number: 7683418Abstract: The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has a thickness of less than about 15 ?; forming an oxygen diffusion barrier atop the layer of metal atoms, wherein the non-oxidizing atmosphere is maintained; forming a gate conductor atop the oxygen diffusion barrier; and annealing the layer of metal atoms and the dielectric layer, wherein the layer of metal atoms reacts with the dielectric layer to provide a continuous metal oxide layer having a dielectric constant ranging from about 25 to about 30 and a thickness less than about 15 ?.Type: GrantFiled: November 25, 2008Date of Patent: March 23, 2010Assignee: International Business Machines CorporationInventors: Dae-Gyu Park, Oleg G. Gluschenkov, Michael A. Gribelyuk, Kwong Hon Wong
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Patent number: 7569848Abstract: Compressive or tensile materials are selectively introduced beneath and in alignment with spacer areas and adjacent to channel areas of a semiconductor substrate to enhance or degrade electron and hole mobility in CMOS circuits. A process entails steps of creating dummy spacers, forming a dielectric mandrel (i.e., mask), removing the dummy spacers, etching recesses into the underlying semiconductor substrate, introducing a compressive or tensile material into a portion of each recess, and filling the remainder of each recess with substrate material.Type: GrantFiled: February 28, 2006Date of Patent: August 4, 2009Assignee: International Business Machines CorporationInventors: Michael P. Belyansky, Bruce B. Doris, Oleg G. Gluschenkov
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Patent number: 7560328Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate, a first layered stack atop the substrate, the first layered stack comprising a first Si-containing portion of the substrates a compressive layer atop the Si-containing portion of the substrate, and a semiconducting silicon layer atop the compressive layer; and a second layered stack atop the substrate, the second layered stack comprising a second-silicon containing layer portion of the substrate, a tensile layer atop the second Si-containing portion of the substrate, and a second semiconducting silicon-layer atop the tensile layer.Type: GrantFiled: March 30, 2007Date of Patent: July 14, 2009Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Omer H. Dokumaci, Oleg G. Gluschenkov, Huilong Zhu
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Publication number: 20090101993Abstract: The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has a thickness of less than about 15 ?; forming an oxygen diffusion barrier atop the layer of metal atoms, wherein the non-oxidizing atmosphere is maintained; forming a gate conductor atop the oxygen diffusion barrier; and annealing the layer of metal atoms and the dielectric layer, wherein the layer of metal atoms reacts with the dielectric layer to provide a continuous metal oxide layer having a dielectric constant ranging from about 25 to about 30 and a thickness less than about 15 ?.Type: ApplicationFiled: November 25, 2008Publication date: April 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dae-Gyu Park, Oleg G. Gluschenkov, Michael A. Gribelyuk, Kwong Hon Wong
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Patent number: 7521345Abstract: The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has a thickness of less than about 15 ?; forming an oxygen diffusion barrier atop the layer of metal atoms, wherein the non-oxidizing atmosphere is maintained; forming a gate conductor atop the oxygen diffusion barrier; and annealing the layer of metal atoms and the dielectric layer, wherein the layer of metal atoms reacts with the dielectric layer to provide a continuous metal oxide layer having a dielectric constant ranging from about 25 to about 30 and a thickness less than about 15 ?.Type: GrantFiled: July 24, 2007Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: Dae-Gyu Park, Oleg G. Gluschenkov, Michael A. Gribelyuk, Kwong H. Wong
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Publication number: 20080237720Abstract: Semiconductor structure formed on a substrate and process of forming the semiconductor. The semiconductor includes a plurality of field effect transistors having a first portion of field effect transistors (FETS) and a second portion of field effect transistors. A first stress layer has a first thickness and is configured to impart a first determined stress to the first portion of the plurality of field effect transistors. A second stress layer has a second thickness and is configured to impart a second determined stress to the second portion of the plurality of field effect transistors.Type: ApplicationFiled: September 28, 2007Publication date: October 2, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce B. Doris, Oleg G. Gluschenkov, Huilong Zhu
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Publication number: 20080233687Abstract: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.Type: ApplicationFiled: June 4, 2008Publication date: September 25, 2008Applicant: International Business Machines CorporationInventors: Huajie Chen, Omer H. Dokumaci, Oleg G. Gluschenkov, Werner A. Rausch
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Publication number: 20080230840Abstract: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.Type: ApplicationFiled: June 4, 2008Publication date: September 25, 2008Applicant: International Business Machines CorporationInventors: Huajie Chen, Omer H. Dokumaci, Oleg G. Gluschenkov, Werner A. Rausch
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Patent number: 7402870Abstract: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.Type: GrantFiled: October 12, 2004Date of Patent: July 22, 2008Assignee: International Business Machines CorporationInventors: Huajie Chen, Omer H. Dokumaci, Oleg G. Gluschenkov, Werner A. Rausch
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Patent number: 7396714Abstract: A process is provided for making a PFET and an NFET. Areas in a first semiconductor region adjacent to a gate stack are recessed. A lattice-mismatched semiconductor layer is grown in the recesses to apply a strain to the channel region of the PFET adjacent thereto. A layer of the first semiconductor material can be grown over the lattice-mismatched semiconductor layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.Type: GrantFiled: June 18, 2007Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: Huajie Chen, Dureseti Chidambarrao, Oleg G. Gluschenkov, An L. Steegen, Haining S. Yang
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Patent number: 7291528Abstract: A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.Type: GrantFiled: March 16, 2005Date of Patent: November 6, 2007Assignee: International Business Machines CorporationInventors: Huajie Chen, Dureseti Chidambarrao, Oleg G. Gluschenkov, An L. Steegen, Haining S. Yang
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Patent number: 7285826Abstract: Semiconductor structure formed on a substrate and process of forming the semiconductor. The semiconductor includes a plurality of field effect transistors having a first portion of field effect transistors (FETS) and a second portion of field effect transistors. A first stress layer has a first thickness and is configured to impart a first determined stress to the first portion of the plurality of field effect transistors. A second stress layer has a second thickness and is configured to impart a second determined stress to the second portion of the plurality of field effect transistors.Type: GrantFiled: October 6, 2005Date of Patent: October 23, 2007Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Oleg G. Gluschenkov, Huilong Zhu