Abstract: A semiconductor structure comprises at least one first nanosheet transistor and at least one second nanosheet transistor disposed on a dielectric layer. The first nanosheet transistor comprises at least one first source/drain region disposed on a side of the first nanosheet transistor. The second nanosheet transistor comprises at least one second source/drain region disposed on a side of the second nanosheet transistor. The second source/drain region has a larger dimension along a given direction than a dimension of the first source/drain region along the given direction. One of a dielectric fill layer and an air gap is disposed in the dielectric layer and under the second source/drain region. A semiconductor layer is disposed under the second source/drain region, in the dielectric layer and around the one of the dielectric fill layer and the air gap.

Abstract: A semiconductor device comprises a gate cut portion disposed between a first gate region and a second gate region. The gate cut portion comprises a dielectric liner layer disposed around a vacant area. The dielectric liner layer encloses the vacant area, and the gate cut portion isolates the first gate region from the second gate region.

Abstract: A method to co-integrate a metal trench cut for aggressively scaled contact tip-to-tip and wrap-around-contact formation is provided. A semiconductor device made from the method is also provided in which a metal trench cut region and wrap-around-contacts are present.

Abstract: A semiconductor structure comprises a substrate defining a first axis and a second axis in orthogonal relation to the first axis, first and second nanosheet stacks disposed on the substrate, a gate structure on each of the first and second nanosheet stacks, a source/drain region adjacent each of the first and second nanosheet stacks, a wrap-around contact disposed about each source/drain region and an isolator pillar disposed between the wrap-around contacts.

Abstract: A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a bottom electrode and a top electrode separated by a dielectric film. A portion of the dielectric film directly above the bottom electrode may be doped and crystalline. The semiconductor structure may include a stud below and in electrical contact with the bottom electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

Abstract: A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a first electrode and a second electrode separated by a dielectric film. A portion of the dielectric film directly above the first electrode may be crystalline. The semiconductor structure may include a stud below and in electrical contact with the first electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

Abstract: An integrated short channel omega gate FinFET and long channel FinFET semiconductor device includes a first fin and second fin on a buried oxide (BOX) layer. The BOX layer includes a fin well outside and substantially adjoining a footprint of a respective fin. A first gate dielectric layer is upon the second fin and a second gate dielectric layer is upon the first dielectric layer. The BOX layer further includes an undercut below the first fin that exposes a portion of a bottom surface of the first fin. An omega-gate is around the first fin. A tri-gate is upon the second gate dielectric layer over the second fin.

Abstract: A Josephson Junction qubit device is provided. The device includes a substrate of silicon material. The device includes first and second electrodes of superconducting metal. The device may include a nanowire created by direct ion implantation on to the silicon material to connect the first and second electrodes. The device may include first and second superconducting regions created by direct ion implantation on to the silicon material, the first superconducting region connecting the first electrode and the second superconducting region connecting the second electrode, with a silicon channel formed by a gap between the first and second superconducting regions.

Abstract: A semiconductor device includes a first field effect transistor (FET) and a second FET arranged under the first FET to form a stack on the frontside of a wafer. A Middle of Line (MOL) contact has a first end connected to a source or drain of the first FET, and a second end connected to a first voltage node. A direct backside contact is connected to a backside power delivery network, the direct backside contact has a first end connected to a source or drain of the second FET, and a second end connected to a second voltage node. A Back End of Line (BEOL) layer has an input signal line and an output signal line. A gate region connects the MOL contact to the input signal line at the BEOL. The first FET and the second FET are connected through the MOL contact to the output signal line.

Abstract: A semiconductor structure includes a gate region, a source/drain region, and a nanosheet semiconductor layer extending continuously across the gate region and the source/drain region. The nanosheet semiconductor layer includes a first portion in the gate region and a second portion in the source/drain region. The source/drain region includes a cladded epitaxial layer wrapping around the second portion of the nanosheet semiconductor layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a field effect transistor (FET) structure having a source/drain (S/D) region between channel regions, primary epitaxy disposed in the S/D region and a backside contact disposed in contact with and gouging into the primary epitaxy.

Abstract: A semiconductor device includes a transistor structure comprising a plurality of source/drain regions. Base portions of the plurality of source/drain regions correspond to a second side of the semiconductor device opposite to a first side of the semiconductor device. A plurality of metal lines are disposed on the second side of the semiconductor device, wherein the plurality of metal lines comprise at least a first metal line and a second metal line. At least one dielectric layer is disposed between the first metal line and the second metal line.

Abstract: A semiconductor structure includes a first metallization layer having a first plurality of metal containing lines, and a second metallization layer located above the first metallization layer. The second metallization layer includes a second plurality of metal containing lines. A first group of the second plurality of metal containing lines is disposed within the first metallization layer. The first group of the second plurality of metal containing lines is isolated from the first metallization layer by a dielectric barrier layer.

Abstract: An approach to provide a semiconductor structure for a phase change memory cell with a first liner material surrounding a sidewall of a hole in a dielectric material where the hole in the dielectric is on a bottom electrode in the dielectric material. The semiconductor structure includes a layer of a second liner material on the first liner material, where the second liner material has an improved contact resistance to a phase change material. The semiconductor structure includes the phase change material abutting the layer of the second liner material on the first liner material. The phase change material fills the hole in the dielectric material. The second liner material that is between the phase change material and the first liner material provides a lower contact resistivity with the phase change material in the crystalline phase than the first liner material.

Abstract: Semiconductor devices and methods of making the same include a first lower device and a second lower device on a substrate. A first upper device is over the first lower device and a second upper device is over the second lower device. A first lower contact extends from a height above the first upper device and makes electrical contact with a top surface and a sidewall surface of the first lower device. A second lower contact extends from a height above the second upper device and makes electrical contact with a top surface and a sidewall surface of the second lower device. An insulating barrier is between the first lower contact and the second lower contact.

Abstract: A semiconductor structure that includes a channel region comprising vertically stacked channels of at least two III-V semiconductor material layers having a two dimensional electron gas regions at an interface of the at least two III-V semiconductor material layers; a gate all around (GAA) geometry gate structure present on the channel region; and source and drain regions on opposing sides of the channel region.

Abstract: A semiconductor structure is presented including source/drain (S/D) epitaxial growth formed over a bottom dielectric isolation region, at least one first semiconductor layer disposed within the S/D epitaxial growth in a S/D region and at least one second semiconductor layer disposed partially within a gate region. The at least one second semiconductor layer extends from the gate region into a spacer region to enable a connection to the S/D epitaxial growth. The semiconductor structure further includes a first region with adjacent devices exhibiting a first Contacted gate Poly Pitch (CPP) defining a first gate-to-gate space and a second region with adjacent devices exhibiting a second CPP defining a second gate-to-gate space, where adjacent devices exhibiting the first CPP have a smaller gate-to-gate canyon than the adjacent devices exhibiting the second CPP such that the second gate-to-gate space is greater than the first gate-to-gate space.

Abstract: A microelectronic structure including a stacked transistor having a lower transistor and an upper transistor. A shared contact in contact with a lower source/drain of the first lower transistor and an upper source/drain of the upper transistor. The shared contact includes a silicide layer, a metal plug layer, and a conductive metal layer.

Abstract: A microelectronics device including a gate region located adjacent to a source/drain region. A contact located above the source/drain region, where the contact has a bottom section, a middle section and top section, wherein the sidewalls of the bottom section, the middle section, and the top section of the contact are tapered towards a center Y-axis of the contact. A gate contact located above the gate region, where the gate contact has tapered sidewalls towards a center Y-axis of the gate contact. The gate contact is adjacent to the contact. The tapering of the sidewalls of the gate contact is inverse to the tapering of the sidewalls of the contact.

Abstract: A first and a second nanosheet stack, a first source drain to the first nanosheet stack, a carrier wafer bonded to an upper surface, a bottom source drain contact located on a bottom surface of the first source drain, an epitaxial region between the bottom source drain contact and the first source drain, a second source drain adjacent to the second nanosheet stack and a top source drain contact located on an upper surface of the second source drain, the bottom source drain contact and the top source drain contact on opposite sides. Forming a first and a second nanosheet stack, forming an upper top source drain contact to first source drain adjacent to the first nanosheet stack, bonding a carrier wafer to an upper surface and forming a bottom source drain contact to a lower horizontal surface of a second source drain adjacent to the second nanosheet stack.