Patents by Inventor Oleg Laboutin

Oleg Laboutin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230097643
    Abstract: A high electron mobility transistor comprising a nucleation layer having a first lattice constant, a back-barrier layer having a second lattice constant and a stress management layer having a third lattice constant which is larger than both first and second lattice constants. The stress management layer compensates some or all of the stress due to the lattice mismatch between the nucleation layer and back barrier layer so that the resulting structure experiences less bow and warp.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 30, 2023
    Applicant: IQE plc
    Inventors: Felix Kaess, Chen-Kai KAO, Oleg LABOUTIN
  • Patent number: 11133408
    Abstract: A passivated semiconductor device structure includes a III-nitride structure and a passivation layer. The III-nitride structure includes a high electron mobility transistor (HEMT). The passivation layer includes a dielectric, which is formed over the structure to provide passivation and forms an interface with the structure. The interface provides a transition between the structure and the dielectric having a thickness of at least two atomic layers. The interface also has a characteristic density of interface states less than a reference density of interface states that corresponds to a thickness of at most one atomic layer. The transition, which constitutes a rough interface, allows a relatively low density of interface states, and thus improves high-frequency performance of the device structure.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: September 28, 2021
    Assignee: IQE plc
    Inventors: Oleg Laboutin, Xiang Gao, Hugues Marchand
  • Publication number: 20210043760
    Abstract: A passivated semiconductor device structure includes a III-nitride structure and a passivation layer. The III-nitride structure includes a high electron mobility transistor (HEMT). The passivation layer includes a dielectric, which is formed over the structure to provide passivation and forms an interface with the structure. The interface provides a transition between the structure and the dielectric having a thickness of at least two atomic layers. The interface also has a characteristic density of interface states less than a reference density of interface states that corresponds to a thickness of at most one atomic layer. The transition, which constitutes a rough interface, allows a relatively low density of interface states, and thus improves high-frequency performance of the device structure.
    Type: Application
    Filed: August 6, 2019
    Publication date: February 11, 2021
    Inventors: Oleg Laboutin, Xiang Gao, Hugues Marchand
  • Patent number: 10580871
    Abstract: Nucleation layers for growth of III-nitride structures, and methods for growing the nucleation layers, are described herein. A semiconductor can include a silicon substrate and a nucleation layer over the silicon substrate. The nucleation layer can include silicon and deep-level dopants. The semiconductor can include a III-nitride layer formed over the nucleation layer. At least one of the silicon substrate and the nucleation layer can include ionized contaminants. In addition, a concentration of the deep-level dopants is at least as high as a concentration of the ionized contaminants.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: March 3, 2020
    Assignee: IQE plc
    Inventors: Oleg Laboutin, Chen-Kai Kao, Chien-Fong Lo, Wayne Johnson, Hugues Marchand
  • Publication number: 20180277639
    Abstract: Nucleation layers for growth of III-nitride structures, and methods for growing the nucleation layers, are described herein. A semiconductor can include a silicon substrate and a nucleation layer over the silicon substrate. The nucleation layer can include silicon and deep-level dopants. The semiconductor can include a III-nitride layer formed over the nucleation layer. At least one of the silicon substrate and the nucleation layer can include ionized contaminants. In addition, a concentration of the deep-level dopants is at least as high as a concentration of the ionized contaminants.
    Type: Application
    Filed: March 12, 2018
    Publication date: September 27, 2018
    Inventors: Oleg Laboutin, Chen-Kai Kao, Chien-Fong Lo, Wayne Johnson, Hugues Marchand
  • Patent number: 9917156
    Abstract: Nucleation layers for growth of III-nitride structures, and methods for growing the nucleation layers, are described herein. A semiconductor can include a silicon substrate and a nucleation layer over the silicon substrate. The nucleation layer can include silicon and deep-level dopants. The semiconductor can include a III-nitride layer formed over the nucleation layer. At least one of the silicon substrate and the nucleation layer can include ionized contaminants. In addition, a concentration of the deep-level dopants is at least as high as a concentration of the ionized contaminants.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: March 13, 2018
    Assignee: IQE, plc
    Inventors: Oleg Laboutin, Chen-Kai Kao, Chien-Fong Lo, Wayne Johnson, Hugues Marchand
  • Publication number: 20180069085
    Abstract: Nucleation layers for growth of III-nitride structures, and methods for growing the nucleation layers, are described herein. A semiconductor can include a silicon substrate and a nucleation layer over the silicon substrate. The nucleation layer can include silicon and deep-level dopants. The semiconductor can include a III-nitride layer formed over the nucleation layer. At least one of the silicon substrate and the nucleation layer can include ionized contaminants. In addition, a concentration of the deep-level dopants is at least as high as a concentration of the ionized contaminants.
    Type: Application
    Filed: September 2, 2016
    Publication date: March 8, 2018
    Inventors: Oleg Laboutin, Chen-Kai Kao, Chien-Fong Lo, Wayne Johnson, Hugues Marchand
  • Publication number: 20170170283
    Abstract: A III-nitride structure can include a silicon substrate, a nucleation layer over the silicon substrate, and a carbon-doped buffer layer over the nucleation layer. The carbon-doped buffer layer can include a III-nitride material and a concentration of carbon that is greater than 1×1020 cm?3. The III-nitride structure can include a III-nitride channel layer over the carbon-doped buffer layer and a III-nitride barrier layer over the III-nitride channel layer. The carbon doping to a carbon concentration greater than 1×1020 cm?3 can increase the compressive stress in the III-nitride structure.
    Type: Application
    Filed: December 5, 2016
    Publication date: June 15, 2017
    Inventors: Oleg Laboutin, Chen-Kai Kao, Chien-Fong Lo, Hugues Marchand, Rodney Pelzel
  • Patent number: 9076812
    Abstract: An iron-doped high-electron-mobility transistor (HEMT) structure includes a substrate, a nucleation layer over the substrate, and a buffer layer over the nucleation layer. The gallium-nitride buffer layer includes a iron-doping-stop layer having a concentration of iron that drops from a juncture with an iron-doped component of the buffer layer over a thickness that is relatively small compared to that of the iron-doped component. The iron-doping-stop layer is formed at lower temperature compared to the temperature at which the iron-doped component is formed. The iron-doped HEMT structure also includes a channel layer over the buffer layer. A carrier-supplying barrier layer is formed over the channel layer.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: July 7, 2015
    Assignee: IQE KC, LLC
    Inventors: Oleg Laboutin, Yu Cao, Wayne Johnson
  • Publication number: 20150001582
    Abstract: An iron-doped high-electron-mobility transistor (HEMT) structure includes a substrate, a nucleation layer over the substrate, and a buffer layer over the nucleation layer. The gallium-nitride buffer layer includes a iron-doping-stop layer having a concentration of iron that drops from a juncture with an iron-doped component of the buffer layer over a thickness that is relatively small compared to that of the iron-doped component. The iron-doping-stop layer is formed at lower temperature compared to the temperature at which the iron-doped component is formed. The iron-doped HEMT structure also includes a channel layer over the buffer layer. A carrier-supplying barrier layer is formed over the channel layer.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 1, 2015
    Applicant: IQE KC, LLC
    Inventors: Oleg Laboutin, Yu Cao, Wayne Johnson
  • Publication number: 20140167058
    Abstract: An epitaxial structure on a substrate includes a gallium nitride buffer layer over the substrate and a graded channel layer over the gallium nitride layer. The graded channel layer consists essentially of InxGa1-xN wherein the value of x gets smaller from a first surface of the channel layer proximate to a buffer layer to a second surface remote from the buffer layer.
    Type: Application
    Filed: August 22, 2013
    Publication date: June 19, 2014
    Applicant: IQE, KC, LLC
    Inventors: Oleg Laboutin, Yu Cao, Wayne Johnson
  • Publication number: 20140151712
    Abstract: An epitaxial structure, such as an enhancement-mode high electron mobility transistor (HEMT) includes a first barrier layer over an aluminum gallium nitride channel layer. The first barrier layer is formed at a first temperature and is overlaid by a second barrier layer formed at a second temperature that is lower than that of the first temperature. The first barrier layer acts as an etch stop when forming a gate recess in the second barrier layer by a wet or dry etching.
    Type: Application
    Filed: June 7, 2013
    Publication date: June 5, 2014
    Inventors: Yu Cao, Oleg Laboutin, Wayne Johnson
  • Publication number: 20130341635
    Abstract: An epitaxial structure and a high electron mobility transistor (HEMT) employing the epitaxial structure includes a first spacer layer over a channel layer, a first barrier layer over the first spacer layer, and a second spacer layer over the first barrier layer.
    Type: Application
    Filed: June 7, 2013
    Publication date: December 26, 2013
    Inventors: Yu Cao, Oleg Laboutin, Wayne Johnson