Abstract: Frequency synthesizers having reduced phase noise and a small step size. One example can provide frequency synthesizers having low phase noise by eliminating dividers in a feedback path and instead employing frequency converters, such as mixers. Step size can be further reduced by providing frequency converters in a reference signal feedforward path. Acquisition time can be decreased by employing a fast-acquisition phase-locked loop that is switched out after acquisition in favor of a low phase-noise phase-locked loop. Another example can reduce phase noise by employing a YIG oscillator. To improve acquisition time, a first, faster phase-locked loop can be used to lock to a signal before switching to a second, slower phase-locked loop that includes the YIG oscillator. Another example can provide low noise by including phase-locked loops that operate in a frequency range having low thermal noise while a frequency of an output signal varies over a wide range.

Abstract: Frequency synthesizers having reduced phase noise and a small step size. One example can provide frequency synthesizers having low phase noise by eliminating dividers in a feedback path and instead employing frequency converters, such as mixers. Step size can be further reduced by providing frequency converters in a reference signal feedforward path. Acquisition time can be decreased by employing a fast-acquisition phase-locked loop that is switched out after acquisition in favor of a low phase-noise phase-locked loop. Another example can reduce phase noise by employing a YIG oscillator. To improve acquisition time, a first, faster phase-locked loop can be used to lock to a signal before switching to a second, slower phase-locked loop that includes the YIG oscillator. Another example can provide low noise by including phase-locked loops that operate in a frequency range having low thermal noise while a frequency of an output signal varies over a wide range.

Abstract: An apparatus and method for building and operating of a YIG-based filter-attenuator module with closed-loop control. The module combines both signal filtering and amplitude control functions by utilizing an yttrium-iron-garnet (YIG) resonator. A technique for a closed-loop calibration and control also disclosed. This apparatus and method provides a cost effective harmonic rejection/amplitude control solution for microwave test-and-measurement instruments such as signal generators and spectrum analyzers.

Abstract: A dual-resonator YIG oscillator with a main YIG resonator and a stabilizing YIG resonator both suspended in a common magnetic field. The main YIG resonator takes on the high-Q factor aspects of the oscillator, while the stabilizing YIG resonator helps stabilize the operation of the main YIG resonator, and also allows the main YIG resonator operate at higher magnetic field strengths, achieving higher frequency operation. The stabilizing YIG resonator also enables the oscillator's active device to operate in a more linear, lower phase noise, regime. As compared to conventional YIG oscillators, the disclosed dual resonator YIG oscillator provides significant performance improvements, such as higher frequency operation, lower power consumption, higher tuning speed, and lower phase noise.

Abstract: An improved noise-corrected phase-locked loop frequency synthesizer configured to reduce noise, such as phase noise and spurious signals, without the use of switching circuits. The synthesizer uses a phase shifter device configured to accept a noise containing frequency signal from a voltage controlled oscillator (VCO) circuit, such as an integer-N single loop PLL synthesizer, as well as noise reducing control signals from a noise detecting sensor or circuit, and output a noise reduced VCO frequency signal. In some embodiments, the noise reducing sensor may be formed from a second, lower noise, phase locked loop circuit. The frequency synthesizer circuit, noise detecting sensor, and the phase shifter device are configured to all run continuously, with the noise reducing sensor and frequency shifter continually acting to reduce noise, produced by higher noise integer-N PLL frequency synthesizer.

Abstract: A low phase noise PLL synthesizer is described in which an initial tuning mechanism uses a conventional divider loop to lock a VCO to a desired output frequency. Once initial lock is achieved, the divider loop is switched out of the circuit in favor of a low phase noise mixer loop. The reference frequency source for the low phase noise loop includes a mixer/divider up-conversion chain at the output of a direct digital synthesizer. This permits fine frequency resolution from the DDS but maintains a high phase detector comparison frequency and therefore fast frequency switching speed.

Abstract: A phase-locked loop (PLL) frequency synthesizer includes a phase detector, a low pass filter coupled to the phase detector, an amplifier coupled to the low pass filter, a voltage controlled oscillator (VCO) coupled to the amplifier, a power splitter coupled to the VCO, and a switch configured to select between a first branch and a second branch through which to couple the power splitter to the phase detector. The first branch includes a frequency divider while the second branch includes a mixer. The PLL frequency synthesizer also includes a frequency accuracy indicator that compares a frequency in the first branch with a frequency generated in the second branch, and confirms that the PLL frequency synthesizer is locked to a desired frequency upon receiving a phase lock signal, if the frequency generated in the first branch is the same as the frequency generated in the second branch.

Abstract: A low phase noise PLL synthesizer is described in which an initial tuning mechanism uses a conventional divider loop to lock a VCO to a desired output frequency. Once initial lock is achieved, the divider loop is switched out of the circuit in favor of a low phase noise mixer loop. The local oscillator signal for the mixer is derived from the same low phase noise source as the phase comparison frequency.

Abstract: A low phase noise PLL synthesizer is described in which an initial tuning mechanism uses a conventional divider loop to lock a VCO to a desired output frequency. Once initial lock is achieved, the divider loop is switched out of the circuit in favor of a low phase noise mixer loop. The local oscillator signal for the mixer is derived from the same low phase noise source as the phase comparison frequency.