Patents by Inventor Olfat Younis

Olfat Younis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Processor architecture for processing variable length instruction words
    Patent number: 9104426
    Abstract: A LIW processor comprises multiple execution units. The multiple execution units of the processor are divided into groups, and an input instruction word can contain instructions for one execution unit in each of the groups. The processor is optimized for use in signal processing operations, in that the multiple execution units of the processor are divided into groups which do not place significant restrictions on the desirable uses of the processor, because it has been determined that, in signal processing applications, it is not usually necessary for certain execution units to operate simultaneously. These execution units can therefore be grouped together, in such a way that only one of them can operate at a particular time, without significantly impacting on the operation of the device. An array is formed from multiple interconnected processors of this type.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: August 11, 2015
    Assignee: Intel Corporation
    Inventors: Andrew Duller, Gajinder Singh Panesar, Peter Claydon, William Robbins, Andrew Kuligowski, Olfat Younis
  • Processor Architecture
    Publication number: 20080065859
    Abstract: A LIW processor comprises multiple execution units. The multiple execution units of the processor are divided into groups, and an input instruction word can contain instructions for one execution unit in each of the groups. The processor is optimised for use in signal processing operations, in that the multiple execution units of the processor are divided into groups which do not place significant restrictions on the desirable uses of the processor, because it has been determined that, in signal processing applications, it is not usually necessary for certain execution units to operate simultaneously. These execution units can therefore be grouped together, in such a way that only one of them can operate at a particular time, without significantly impacting on the operation of the device. An array is formed from multiple interconnected processors of this type.
    Type: Application
    Filed: November 1, 2007
    Publication date: March 13, 2008
    Inventors: Andrew Duller, Gajinder Panesar, Peter Claydon, William Robbins, Andrew Kuligowski, Olfat Younis
  • Processor architecture
    Publication number: 20060155958
    Abstract: A LIW processor comprises multiple execution units. The multiple execution units of the processor are divided into groups, and an input instruction word can contain instructions for one execution unit in each of the groups. The processor is optimised for use in signal processing operations, in that the multiple execution units of the processor are divided into groups which do not place significant restrictions on the desirable uses of the processor, because it has been determined that, in signal processing applications, it is not usually necessary for certain execution units to operate simultaneously. These execution units can therefore be grouped together, in such a way that only one of them can operate at a particular time, without significantly impacting on the operation of the device. An array is formed from multiple interconnected processors of this type.
    Type: Application
    Filed: December 2, 2005
    Publication date: July 13, 2006
    Inventors: Andrew Duller, Gajinder Panesar, Peter Claydon, William Robbins, Andrew Kuligowski, Olfat Younis