Patents by Inventor Olga Pavlovna POPE

Olga Pavlovna POPE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-phase clock generation circuit
    Patent number: 10659059
    Abstract: A multi-phase clock circuit includes a first delay circuit, a second delay circuit, a third delay circuit, a first clock mixer circuit, and a second clock mixer circuit. The first, second, and third delay circuits are coupled in series. The first clock mixer circuit includes a first input and a second input. The first input is coupled to an output of the first delay circuit. The second input is coupled to an output of the second delay circuit. The second clock mixer circuit also includes a first input and a second input. The first input of the second clock mixer circuit is coupled to an output of the second delay circuit. The second input of the second clock mixer circuit is coupled to an output of the third delay circuit.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: May 19, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Robert Floyd Payne, Olga Pavlovna Pope
  • MULTI-PHASE CLOCK GENERATION CIRCUIT
    Publication number: 20200106450
    Abstract: A multi-phase clock circuit includes a first delay circuit, a second delay circuit, a third delay circuit, a first clock mixer circuit, and a second clock mixer circuit. The first, second, and third delay circuits are coupled in series. The first clock mixer circuit includes a first input and a second input. The first input is coupled to an output of the first delay circuit. The second input is coupled to an output of the second delay circuit. The second clock mixer circuit also includes a first input and a second input. The first input of the second clock mixer circuit is coupled to an output of the second delay circuit. The second input of the second clock mixer circuit is coupled to an output of the third delay circuit.
    Type: Application
    Filed: June 27, 2019
    Publication date: April 2, 2020
    Inventors: Robert Floyd PAYNE, Olga Pavlovna POPE