Abstract: A method in which connectivity tests of integrated circuit structures in a die are performed. The connectivity tests are performed at a first level of the die. Potential defect locations are identified in the die indicating via locations susceptible to systematic failure due to via opens or via shorts. The potential defect locations are translated to via locations for a second level of the die. The second level is below the first level. After translating the hot spot, the second level is inspected for defects. The via locations on the first level are inspected for defects. All defects for the second level are translated to the via locations for the first level. A net trace of defects is created using prior level subtraction of the translated defects for the second level and the defects for the first level.

Abstract: A method of inspecting semiconductors and a semiconductor inspection system are disclosed. In an embodiment, the method comprises directing a charged particle beam onto a semiconductor device at an angle in a range between five degrees and eighty-five degrees from a normal to a top surface of the semiconductor; scanning the particle beam across a field of the semiconductor device; adjusting the semiconductor to maintain the particle beam at a defined focus on the semiconductor while scanning the particle beam across the field of the semiconductor device; detecting secondary and backscattered electrons from the semiconductor; and processing the detected secondary and backscattered electrons to inspect for defined conditions of the semiconductor. In an embodiment, the particle beam is maintained at the defined focus on the semiconductor device by controlling the position of the semiconductor device relative to a beam emitter that emits the particle beam.

Abstract: A method in which connectivity tests of integrated circuit structures in a die are performed. The connectivity tests are performed at a first level of the die. Potential defect locations are identified in the die indicating via locations susceptible to systematic failure due to via opens or via shorts. The potential defect locations are translated to via locations for a second level of the die. The second level is below the first level. After translating the hot spot, the second level is inspected for defects. The via locations on the first level are inspected for defects. All defects for the second level are translated to the via locations for the first level. A net trace of defects is created using prior level subtraction of the translated defects for the second level and the defects for the first level.

Abstract: A SRAM-like electron beam inspection (EBI) structure and method for determining defects in integrated circuits inline during the production process at a level that enables earlier detection during fabrication. Initial layers, such as active layer, poly gate and contact of an IC are first fabricated, and a conductive mesh with horizontal components is provided above the contact layers connecting contact nodes of the contact layers. Voltage contrast is observed during EBI to detect short-circuits, open-circuits, or leakage currents formed between the horizontal components of the conductive mesh and metallized islands placed therebetween.

Abstract: A method for designing, a structure, method of inspecting and a computer system for designing voltage contrast integrated circuit characterization. The design method includes selecting a design level of a mask design shapes file; selecting a region of the design level having an open region having no design shapes and an adjacent circuit region having circuit design shapes; selecting a sub-region of the circuit region adjacent to the open region; copying design shapes of the sub-region to generate a characterization cell identical to the sub-region; modifying the characterization cell to generate a passive voltage contrast characterization cell; and placing the passive voltage contrast characterization cell into the open region adjacent to the sub-region to generate a modified design level.

Abstract: A semiconductor substrate inspection system includes an e-beam inspection system configured to deliver electrons to a specimen semiconductor substrate. A sensor is configured to detect reflected electrons that reflect off the surface of the specimen semiconductor substrate. An analysis unit is configured to determine a number of electrons received by the semiconductor substrate, and to determine at least one target region including at least one defect of the semiconductor substrate. A reference image module is in electrical communication with the analysis unit. The reference image module is configured to generate a first digital image having a plurality of pixels, and to adjust a gray-scale level of the pixels included in the target region based on the number electrons included in each pixel to generate a second digital image that excludes the at least one defect.

Abstract: A method for designing, a structure, method of inspecting and a computer system for designing voltage contrast integrated circuit characterization. The design method includes selecting a design level of a mask design shapes file; selecting a region of the design level having an open region having no design shapes and an adjacent circuit region having circuit design shapes; selecting a sub-region of the circuit region adjacent to the open region; copying design shapes of the sub-region to generate a characterization cell identical to the sub-region; modifying the characterization cell to generate a passive voltage contrast characterization cell; and placing the passive voltage contrast characterization cell into the open region adjacent to the sub-region to generate a modified design level.

Abstract: A method including forming a first test structure and a second test structure in electrical contact with an inner buried plate and an outer buried plate, respectively, where the first and second test structures each comprise a deep trench filled with a conductive material, and measuring the voltage of the inner buried plate and the outer buried plate immediately after the formation of a deep trench isolation structure, where the inner buried plate and the outer buried plate are positioned on opposite sides of the deep trench isolation structure.

Abstract: A test structure of a semiconductor wafer includes a series of electrical units connected electrically in series output-to-input in an open loop configuration. The series of electrical units is configured to have alternating output voltages, such that each electrical unit is configured to output a voltage opposite an output voltage of a preceding electrical unit. Each electrical unit is configured to have an output voltage that alternates when an input voltage applied to a first electrical unit in the series of electrical units alternates.

Abstract: Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices.

Abstract: A system and method for improved voltage contrast inspection is disclosed. In one embodiment the temporal response to voltage contrast is considered to find an optimal acquisition time. In another embodiment, multiple optimal acquisition times are identified. The identified acquisition times are used in voltage contrast inspection of semiconductor fabrication, and are well-suited to SOI technology.

Abstract: A semiconductor substrate inspection system includes an e-beam inspection system configured to deliver electrons to a specimen semiconductor substrate. A sensor is configured to detect reflected electrons that reflect off the surface of the specimen semiconductor substrate. An analysis unit is configured to determine a number of electrons received by the semiconductor substrate, and to determine at least one target region including at least one defect of the semiconductor substrate. A reference image module is in electrical communication with the analysis unit. The reference image module is configured to generate a first digital image having a plurality of pixels, and to adjust a gray-scale level of the pixels included in the target region based on the number electrons included in each pixel to generate a second digital image that excludes the at least one defect.

Abstract: Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices.

Abstract: Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices.

Abstract: A method including forming a first test structure and a second test structure in electrical contact with an inner buried plate and an outer buried plate, respectively, where the first and second test structures each comprise a deep trench filled with a conductive material, and measuring the voltage of the inner buried plate and the outer buried plate immediately after the formation of a deep trench isolation structure, where the inner buried plate and the outer buried plate are positioned on opposite sides of the deep trench isolation structure.

Abstract: A method including forming a first test structure and a second test structure in electrical contact with an inner buried plate and an outer buried plate, respectively, where the first and second test structures each comprise a deep trench filled with a conductive material, and measuring the voltage of the inner buried plate and the outer buried plate immediately after the formation of a deep trench isolation structure, where the inner buried plate and the outer buried plate are positioned on opposite sides of the deep trench isolation structure.

Abstract: A system and method for improved voltage contrast inspection is disclosed. In one embodiment the temporal response to voltage contrast is considered to find an optimal acquisition time. In another embodiment, multiple optimal acquisition times are identified. The identified acquisition times are used in voltage contrast inspection of semiconductor fabrication, and are well-suited to SOI technology.

Abstract: A static random access memory (SRAM) test structure includes a p-type source/drain implant region comprising contacts (CAs), wherein the CAs in the p-type source/drain implant region comprise a first plurality of bit line, ground, and node CAs, and wherein the CAs in the p-type source/drain implant region are grounded during an inspection of the SRAM test structure; and an ungrounded region, the ungrounded region being distinct from the p-type source/drain implant region and being ungrounded during the inspection of the SRAM test structure, the ungrounded region comprising contacts (CAs) and rectangular contacts (CArecs) comprising a second plurality of bit line, ground, and node CAs, and further comprising a first plurality of Vdd CAs and rectangular contacts (CArecs), and wherein a CA or CArec in the ungrounded region is grounded during the inspection in the event of a short to a CA in the p-type source/drain implant region.

Abstract: A semiconductor structure including a test structure for detection of a gap in a conductive layer of the semiconductor structure includes a semiconductor substrate; the test structure, the test structure being located on the semiconductor substrate, the test structure comprising a multilayer gate stack, wherein the multilayer gate stack includes a single conductive layer region including: a gate dielectric located on the semiconductor substrate; the conductive layer located on the gate dielectric; and an undoped amorphous silicon layer located on the conductive layer; and wherein the test structure is configured to detect the presence of the gap in the conductive layer.

Abstract: A method of performing inspection alignment point selection for semiconductor devices includes importing, with a computer device, one or more semiconductor design files corresponding to an area of a semiconductor die; aligning a design taken from the one or more semiconductor design files with an image taken from a die of a semiconductor wafer; and selecting an alignment point and recording a portion of the design file corresponding to the alignment point as a master reference image.