Patents by Inventor Oliver EICHINGER
Oliver EICHINGER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088087Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Inventors: Alexander HEINRICH, Michael JUERSS, Konrad ROESL, Oliver EICHINGER, Kok Chai GOH, Tobias SCHMIDT
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Patent number: 11842975Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.Type: GrantFiled: November 11, 2019Date of Patent: December 12, 2023Assignee: Infineon Technologies AGInventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
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Publication number: 20210167034Abstract: A chip arrangement including: a chip including a chip back side; a substrate including a surface with a plating; and a zinc-based solder alloy which attaches the chip back side to the plating on the surface of the substrate, the zinc-based solder alloy including, by weight, 1% to 30% aluminum, 0.5% to 20% germanium, and 0.5% to 20% gallium, wherein a balance of the zinc-based solder alloy is zinc.Type: ApplicationFiled: January 15, 2021Publication date: June 3, 2021Inventors: Manfred MENGEL, Alexander HEINRICH, Steffen ORSO, Thomas BEHRENS, Oliver EICHINGER, Lim FONG, Evelyn NAPETSCHNIG, Edmund RIEDL
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Patent number: 10930614Abstract: A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.Type: GrantFiled: July 26, 2017Date of Patent: February 23, 2021Assignee: Infineon Technologies AGInventors: Manfred Mengel, Alexander Heinrich, Steffen Orso, Thomas Behrens, Oliver Eichinger, Lim Fong, Evelyn Napetschnig, Edmund Riedl
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Publication number: 20200075530Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.Type: ApplicationFiled: November 11, 2019Publication date: March 5, 2020Inventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
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Patent number: 10475761Abstract: A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer.Type: GrantFiled: September 10, 2018Date of Patent: November 12, 2019Assignee: Infineon Technologies AGInventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
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Publication number: 20190006311Abstract: A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer.Type: ApplicationFiled: September 10, 2018Publication date: January 3, 2019Inventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
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Publication number: 20170323865Abstract: A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.Type: ApplicationFiled: July 26, 2017Publication date: November 9, 2017Inventors: Manfred MENGEL, Alexander HEINRICH, Steffen ORSO, Thomas BEHRENS, Oliver EICHINGER, Lim FONG, Evelyn NAPETSCHNIG, Edmund RIEDL
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Patent number: 9735126Abstract: A solder alloy is providing, the solder alloy including zinc, aluminum, magnesium and gallium, wherein the aluminum constitutes by weight 8% to 20% of the alloy, the magnesium constitutes by weight 0.5% to 20% of the alloy and the gallium constitutes by weight 0.5% to 20% of the alloy, the rest of the alloy including zinc.Type: GrantFiled: June 7, 2011Date of Patent: August 15, 2017Assignee: INFINEON TECHNOLOGIES AGInventors: Manfred Mengel, Alexander Heinrich, Steffen Orso, Thomas Behrens, Oliver Eichinger, Lim Fong, Evelyn Napetschnig, Edmund Riedl
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Publication number: 20170025375Abstract: An electric device with a multi-layer contact is disclosed. In an embodiment, the electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.Type: ApplicationFiled: September 30, 2016Publication date: January 26, 2017Inventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
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Patent number: 9490193Abstract: The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.Type: GrantFiled: December 1, 2011Date of Patent: November 8, 2016Assignee: Infineon Technologies AGInventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
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Patent number: 9034751Abstract: A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 ?m. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm2 of surface area of the first main surface and heat is applied to the solder material.Type: GrantFiled: July 18, 2014Date of Patent: May 19, 2015Assignee: Infineon Technologies AGInventors: Alexander Heinrich, Konrad Roesl, Oliver Eichinger
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Publication number: 20140329361Abstract: A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 ?m. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm2 of surface area of the first main surface and heat is applied to the solder material.Type: ApplicationFiled: July 18, 2014Publication date: November 6, 2014Inventors: Alexander Heinrich, Konrad Roesl, Oliver Eichinger
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Patent number: 8802553Abstract: A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 ?m. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm2 of surface area of the first main surface and heat is applied to the solder material.Type: GrantFiled: February 10, 2011Date of Patent: August 12, 2014Assignee: Infineon Technologies AGInventors: Alexander Heinrich, Konrad Roesl, Oliver Eichinger
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Patent number: 8531014Abstract: A method and a system for minimizing carrier stress of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a carrier comprising a mesh coated with a metallic material, and a semiconductor chip disposed over the carrier.Type: GrantFiled: September 27, 2010Date of Patent: September 10, 2013Assignee: Infineon Technologies AGInventors: Manfred Mengel, Oliver Eichinger, Khalil Hosseini, Joachim Mahler
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Publication number: 20130140685Abstract: The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.Type: ApplicationFiled: December 1, 2011Publication date: June 6, 2013Applicant: Infineon Technologies AGInventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
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Publication number: 20120313230Abstract: A solder alloy is providing, the solder alloy including zinc, aluminum, magnesium and gallium, wherein the aluminum constitutes by weight 8% to 20% of the alloy, the magnesium constitutes by weight 0.5% to 20% of the alloy and the gallium constitutes by weight 0.5% to 20% of the alloy, the rest of the alloy including zinc.Type: ApplicationFiled: June 7, 2011Publication date: December 13, 2012Applicant: INFINEON TECHNOLOGIES AGInventors: Manfred MENGEL, Alexander HEINRICH, Steffen ORSO, Thomas BEHRENS, Oliver EICHINGER, Lim FONG, Evelyn NAPETSCHNIG, Edmund RIEDL
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Publication number: 20120208323Abstract: A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 ?m. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm2 of surface area of the first main surface and heat is applied to the solder material.Type: ApplicationFiled: February 10, 2011Publication date: August 16, 2012Applicant: Infineon Technologies AGInventors: Alexander Heinrich, Konrad Roesl, Oliver Eichinger
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Publication number: 20120074568Abstract: A method and a system for minimizing carrier stress of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a carrier comprising a mesh coated with a metallic material, and a semiconductor chip disposed over the carrier.Type: ApplicationFiled: September 27, 2010Publication date: March 29, 2012Inventors: Oliver EICHINGER, Khalil HOSSEINI, Joachim MAHLER, Manfred MENGEL