Abstract: A system for creating a representation of visible space around a machine using a previously determined combined occupancy grid. The system includes a plurality of sensors and an electronic processor. The electronic processor is configured to determine a combined occupancy grid associated with a first time, wherein the combined occupancy grid is determined based on sensor data associated with the first time and received from the plurality of sensors. The electronic processor is also configured to receive, from the plurality of sensors, sensor data associated with a second time and determine a representation of visible space associated with the second time based on the combined occupancy grid associated with the first time and the sensor data associated with the second time. The electronic processor is further configured to control a movement of the machine based on the representation of visible space associated with the second time.

Abstract: System for handling uncertainty associated with a sensor measurement using a previously determined combined occupancy grid. The system includes a plurality of sensors and an electronic processor. The electronic processor is configured to determine a combined occupancy grid associated with a first time, receive a measurement associated with a second time, determine an uncertainty grid including an uncertainty distribution associated with the measurement, and convolute the combined occupancy grid associated with the first time with the uncertainty grid to determine one or more convolution values. Each convolution value is associated with a cell in the uncertainty grid. The electronic processor is configured to assign a first probability to a cell associated with a greatest convolution value, assign a second probability to a cell associated with a mean of the uncertainty distribution, and, using the first probability and the second probability, determine a combined occupancy grid associated with the second time.

Abstract: The invention provides a method of protecting food or beverage material aroma compounds comprising the steps of separating food or beverage material aroma compounds from a food or beverage material, protecting the separated aroma compounds with a protecting group, and storing said protected aroma compounds.

Abstract: The present invention relates to a compound of formula (I1); to a mixture comprising an amount from 86% to 99% by weight measured by quantitative proton-NMR of a compound of formula (IA), (IB), (IC), (ID), (IE), (IF), (IG), (IH) and (IJ); and an edible composition and an edible article comprising them. The invention also relates to processes for their preparation and their use as a savoury and mouthfulness taste enhancer; particularly kokumi and/or umami taste enhancer. Formulae (I?) (IA), (IB), (IC), (ID), (IE), (IF), (IG), (IH), (IJ).

Abstract: A braking system for a vehicle that includes at least one vehicle wheel and a friction brake associated with the vehicle wheel. The friction brake acts during an operation state of the vehicle and/or while the vehicle is in a parked state. The braking system includes an additional mechanical locking device for the vehicle wheel. The mechanical locking device secures the vehicle wheel in a form-fitting manner when the vehicle is in the parked state to prevent the vehicle wheel from rolling.

Abstract: A multi-axial blow-molded packing cushion is a resilient, hollow, thin-walled, generally parallelepiped blow-molded body, having opposite ends, each end defining a groove thereacross. The grooves are each sized and shaped to receive opposite edges of a rectangular opening in a packing insert. Each packing cushion may be snap-fitted into the packing insert rectangular opening by sliding a first end of the packing cushion into a rectangular opening, aligning a first groove defined across the first end of the packing cushion with a first edge of the rectangular opening and pressing down on the packing cushion to snap-fit a second groove defined across a second end of the packing cushion over a second edge of the rectangular opening, with the second grove aligned with the second edge of the rectangular opening. The packing insert, with maintained cushions, is disposed between a packed item and outer packaging, on each item side.

Abstract: The invention provides a method of treating a beverage ingredient extract comprising the steps of: a. filtering a beverage ingredient extract to obtain a beverage ingredient extract retentate and a beverage ingredient extract permeate; b. raising the pH of said beverage ingredient extract retentate to provide a treated beverage ingredient extract retentate; and c. combining said treated beverage ingredient extract retentate with said beverage ingredient extract permeate to generate a recombined ingredient extract.

Abstract: A braking system for a vehicle that includes at least one vehicle wheel and a friction brake associated with the vehicle wheel. The friction brake acts during an operation state of the vehicle and/or while the vehicle is in a parked state. The braking system includes an additional mechanical locking device for the vehicle wheel. The mechanical locking device secures the vehicle wheel in a form-fitting manner when the vehicle is in the parked state to prevent the vehicle wheel from rolling.

Abstract: The present invention relates to a compound of formula (Ii); to a mixture comprising an amount from 86% to 99% by weight measured by quantitative proton-NMR of a compound of formula (IA), (IB), (IC), (ID), (IE), (IF), (IG), (IH) and (IJ); and an edible composition and an edible article comprising them. The invention also relates to processes for their preparation and their use as a savoury and mouthfulness taste enhancer; particularly kokumi and/or umami taste enhancer. Formulae (I?) (IA), (IB), (IC), (ID), (IE), (IF), (IG), (IH), (IJ).

Abstract: A method is disclosed use with a circuit device that includes a circuit having a predetermined voltage-current characteristic and a detector configured to detect a voltage-current relation of the circuit. The method includes using the detector to detect the voltage-current relation of the circuit, and indicating if the detected voltage-current relation differs from the predetermined voltage-current characteristic. A circuit device includes a circuit having a predetermined voltage-current characteristic, and a detector configured to detect a voltage-current relation of the circuit. The circuit device is configured to indicate if the detected voltage-current relation differs from the predetermined voltage-current characteristic.

Abstract: A radar device comprises a test signal generator including a digital harmonic oscillator that generates a digital oscillator signal with a first spectral component; a first digital-to-analog-converter that generates an analog oscillator signal based on the digital oscillator signal. Furthermore, the radar device comprises at least one radar channel receiving the analog oscillator signal during one or more self-tests.

Abstract: A method for producing a semiconductor device is described. In accordance with one example embodiment, the method comprises providing a virtual DUT in the form of a behavior model of the semiconductor device and developing at least one test in a test development environment for an automatic test equipment (ATE). In this case, commands are generated by means of the test development environment, which commands are converted into test signals by means of a software interface, which test signals are fed to the virtual DUT and are processable by the latter. The software interface processes response signals of the virtual DUT and reports information dependent on the response signals back to the test development environment.

Abstract: A compound may include a set of integrated circuits. An integrated circuit, of the set of integrated circuits, may include calibration standards integrated at a silicon layer of the integrated circuit. The integrated circuit may be included in a package, and a calibration standard, of the calibration standards, may be available to at least one port of a set of ports of the integrated circuit.

Abstract: One exemplary embodiment of the present invention relates to a circuit that includes at least one RF signal path for an RF signal and at least one power sensor, which is coupled to the RF signal path and configured to generate a sensor signal representing the power of the RF signal during normal operation of the circuit. The circuit further includes a circuit node for receiving an RF test signal during calibration operation of the circuit. The circuit node is coupled to the at least one power sensor, so that the at least one power sensor receives the RF test signal additionally or alternatively to the RF signal and generates the sensor signal as representing the power of the RF test signal.

Abstract: A test set-up for testing a system-in package with an integrated antenna is described herein. According to one exemplary embodiment, the test set-up includes a carrier with an RF probe arranged thereon and a test socket with resilient electric contacts. The test socket is mounted on the carrier and provides an electric contact to interconnects of the package when it is placed on the test socket. The test socket has an opening which is arranged superjacent to the RF probe.

Abstract: A radar sensor includes a mixer configured to receive an radio frequency (RF) input signal to down-convert the RF input signal into a base-band or intermediate frequency (IF) band, an analog-to-digital converter (ADC), and a signal processing chain coupled between the mixer and the ADC. The radar sensor further includes an oscillator circuit that is configured to generate a test signal. The ADC is coupled to an output of the signal processing chain, and is configured to generate a digital signal by digitizing an output signal of the signal processing chain, the output signal being derived from the test signal. The radar sensor further includes a digital signal processing circuit coupled to the ADC downstream thereof, the digital signal processing circuit being configured to perform a spectral analysis on frequency values of the digital signal.

Abstract: One exemplary embodiment of the present invention relates to a circuit that includes at least one RF signal path for an RF signal and at least one power sensor, which is coupled to the RF signal path and configured to generate a sensor signal representing the power of the RF signal during normal operation of the circuit. The circuit further includes a circuit node for receiving an RF test signal during calibration operation of the circuit. The circuit node is coupled to the at least one power sensor, so that the at least one power sensor receives the RF test signal additionally or alternatively to the RF signal and generates the sensor signal as representing the power of the RF test signal.

Abstract: An integrated circuit is described herein. According to one or more embodiments, the integrated circuit includes a local oscillator with a voltage-controlled oscillator (VCO) that generates a local oscillator signal. Further, the integrated circuit includes a frequency divider coupled to the VCO downstream thereof. The frequency divider provides a frequency-divided local oscillator signal by reducing the frequency of the local oscillator signal by a constant factor. A first test pad of the integrated circuit is configured to receive a reference oscillator signal. Further, the integrated circuit includes a first mixer that receives the reference oscillator signal and the frequency-divided local oscillator signal to down-convert the frequency-divided local oscillator signal.

Abstract: A method for producing a semiconductor device is described. In accordance with one example embodiment, the method comprises providing a virtual DUT in the form of a behavior model of the semiconductor device and developing at least one test in a test development environment for an automatic test equipment (ATE). In this case, commands are generated by means of the test development environment, which commands are converted into test signals by means of a software interface, which test signals are fed to the virtual DUT and are processable by the latter. The software interface processes response signals of the virtual DUT and reports information dependent on the response signals back to the test development environment.

Abstract: A probe card for a wafer tester includes a mother card having a reinforcing element and at least one daughter card which is rigidly connected to the reinforcing element detachably. The mother card includes electrical contacts for producing an electrical connection with the wafer tester. The at least one daughter card includes electrical contact elements for making contact with an electrical circuit on a wafer. In addition, the mother card and the at least one daughter card are electrically detachably connected to one another via an electrical interface.