Abstract: Column packing apparatus are disclosed. Methods of making and using column packing apparatus are also disclosed.

Abstract: Column packing apparatus are disclosed. Methods of making and using column packing apparatus are also disclosed.

Abstract: A method for producing a semiconductor structure including preparing a semiconductor substrate, and generating a lower first, a middle second and an upper third masking layer on a surface of the semiconductor substrate. The method further includes forming at least one first window in the upper third masking layer, structuring the middle second masking layer using the first window for transferring the first window, structuring the lower first masking layer using the first window for transferring the first window, and enlarging the first window to form a second window. The method for further includes restructuring the middle second masking layer using the second window for transferring the second window, structuring the semiconductor substrate, using the structured lower third masking layer, restructuring the lower first masking layer using the second window, and restructuring the semiconductor substrate using the restructured lower third masking layer.

Abstract: A process for introducing structures that have different dimensions, particularly with regard to depth, in which just one lithography level is required, is disclosed. This is achieved by use of a layer stack deposited on a substrate, where one layer in particular is used to store information related to the dimensioning of the different structures. The layer is partially opened up to expose the substrate at locations corresponding to where deep structures are to be formed. Deep structures are subsequently etched into the substrate, after which the layer is opened up at locations corresponding to where shallow structures are to be formed. The latter locations are subsequently etched to the desired depth of the shallower structures. The process can be used instead of conventional the dual damascene technology for the structuring of contact holes and interconnects.

Abstract: An apparatus and method for measuring feature sizes having form birefringence.

Abstract: Disclosed is a method for fabricating a contract hole plane in a memory module with an arrangement of memory cells each having a selection transistor. The methods can be utilized during the production of dynamic random access memory (DRAM) modules.

Abstract: A method for producing a semiconductor structure including preparing a semiconductor substrate, and generating a lower first, a middle second and an upper third masking layer on a surface of the semiconductor substrate. The method further includes forming at least one first window in the upper third masking layer, structuring the middle second masking layer using the first window for transferring the first window, structuring the lower first masking layer using the first window for transferring the first window, and enlarging the first window to form a second window. The method for further includes restructuring the middle second masking layer using the second window for transferring the second window, structuring the semiconductor substrate, using the structured lower third masking layer, restructuring the lower first masking layer using the second window, and restructuring the semiconductor substrate using the restructured lower third masking layer.

Abstract: In order to fabricate a contact hole plane in a memory module with an arrangement of memory cells each having a selection transistor, on a semiconductor substrate with an arrangement of mutually adjacent gate electrode tracks on the semiconductor surface, an insulator layer is formed on the semiconductor surface and a sacrificial layer is subsequently formed on the insulator layer, then material plugs are produced on the sacrificial layer for the purpose of defining contact openings between the mutually adjacent gate electrode tracks, the sacrificial layer is etched to form material plugs with the underlying sacrificial layer blocks, after the production of the vitreous layer with uncovering of the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks, an essentially planar surface being formed, then the sacrificial layer material is etched out from the vitreous layer and the uncovered insulator material is removed above the contact openings on the semiconduct

Abstract: An apparatus (100) for patterning the surface of a semiconductor wafer (130). A stage (148) is coupled to a motor (150) that is adapted to move the stage (148) and a semiconductor wafer (130) in a horizontal direction at a first speed A. A mask (140) is disposed above the semiconductor wafer (130), the mask (140) being coupled to a motor (142) that is adapted to move the mask (140) in a horizontal direction at a second speed B. The ratio of the first and second speeds is different than the magnification factor, which may be other than 1:1 if a lens (120) is used. The mask (140) and the wafer (130) may be moved in the same horizontal direction simultaneously during the exposure process at different speeds B and A, respectively, to provide a magnification or demagnification of the mask (140) pattern onto the wafer (130) surface.

Abstract: A process for introducing structures that have different dimensions, particularly with regard to depth, in which just one lithography level is required, is disclosed. This is achieved by use of a layer stack deposited on a substrate, where one layer in particular is used to store information related to the dimensioning of the different structures. The layer is partially opened up to expose the substrate at locations corresponding to where deep structures are to be formed. Deep structures are subsequently etched into the substrate, after which the layer is opened up at locations corresponding to where shallow structures are to be formed. The latter locations are subsequently etched to the desired depth of the shallower structures. The process can be used instead of conventional the dual damascene technology for the structuring of contact holes and interconnects.

Abstract: A method for removing a carbon-containing polysilane from a semiconductor substrate without stripping the polysilane during manufacture of a semiconductor device, the method entailing the steps in the following order of coating a carbon-containing polysilane on a semiconductor substrate and coating a resist on the polysilane; patterning the resist with exposure and development; transferring the pattern from the resist to the polysilane using an etch process selective to the resist; stripping the resist; transferring the pattern from the polysilane to a hardmask using an etch selective to the hardmask; subjecting the polysilane to thermal or plasma/thermal oxidation to convert the polysilane to silicon oxide; and etching the substrate and stripping off the hardmask.

Abstract: An a&pgr;&pgr;aratus and method for measuring feature sizes having form birefringence.

Abstract: In a method of forming a DRAM cell in a semiconductor substrate, the improvement of maintaining a substantially full trench opening during trench processing comprising: a) forming a pad nitride on the surface of the substrate and reactive ion etching (RIE) a trench vertically to a first depth; b) depositing a nitride layer in the trench; c) filling the trench with a poly silicon fill; d) recess etching the fill to the collar depth; e) oxidizing to transform the exposed nitride layer into a nitrided oxide collar or depositing an oxide on the layer of nitride; f) reactive ion etching to open the bottom oxide; g) stripping the poly fill trench, and performing a nitride etch selective to oxide; h) expanding the trench horizontally by etching lower trench sidewalls and bottom while masking the upper sidewalls; i) forming a buried plate at the bottom of the trench sidewalls; j) forming the node dielectric in the deep trench to grow a collar oxide that consists of a nitrided oxide and a layer of node nitride; k) fil

Abstract: An apparatus (100) for patterning the surface of a semiconductor wafer (130). A stage (148) is coupled to a motor (150) that is adapted to move the stage (148) and a semiconductor wafer (130) in a horizontal direction at a first speed A. A mask (140) is disposed above the semiconductor wafer (130), the mask (140) being coupled to a motor (142) that is adapted to move the mask (140) in a horizontal direction at a second speed B. The ratio of the first and second speeds is different than the magnification factor, which may be other than 1:1 if a lens (120) is used. The mask (140) and the wafer (130) may be moved in the same horizontal direction simultaneously during the exposure process at different speeds B and A, respectively, to provide a magnification or demagnification of the mask (140) pattern onto the wafer (130) surface.

Abstract: A method and apparatus (100) for patterning the surface of a semiconductor wafer (130). A stage (148) is coupled to a motor (150) that is adapted to move the stage (148) and a semiconductor wafer (130) in a horizontal direction at a first speed A. A mask (140) is disposed above the semiconductor wafer (130), the mask (140) being coupled to a motor (142) that is adapted to move the mask (140) in a horizontal direction at a second speed B. The ratio of the first and second speeds is different than the magnification factor, which may be other than 1:1 if a lens (120) is used. The mask (140) and the wafer (130) may be moved in the same horizontal direction simultaneously during the exposure process at different speeds B and A, respectively, to provide a magnification or demagnification of the mask (140) pattern onto the wafer (130) surface.

Abstract: A method for removing polysilane from a semiconductor substrate without stripping during manufacture of a semiconductor device, comprising:

Abstract: A method and apparatus (100) for patterning the surface of a semiconductor wafer (130). A stage (148) is coupled to a motor (150) that is adapted to move the stage (148) and a semiconductor wafer (130) in a horizontal direction at a first speed A. A mask (140) is disposed above the semiconductor wafer (130), the mask (140) being coupled to a motor (142) that is adapted to move the mask (140) in a horizontal direction at a second speed B. The ratio of the first and second speeds is different than the magnification factor, which may be other than 1:1 if a lens (120) is used. The mask (140) and the wafer (130) may be moved in the same horizontal direction simultaneously during the exposure process at different speeds B and A, respectively, to provide a magnification or demagnification of the mask (140) pattern onto the wafer (130) surface.

Abstract: A method for forming a valve metal oxide for semiconductor fabrication in accordance with the present invention is disclosed and claimed. The method includes the steps of providing a semiconductor wafer, depositing a valve metal on the wafer, placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the valve metal to form a metal oxide when a potential difference is provided between the valve metal and the solution and processing the wafer using the metal oxide layer.

Abstract: A method for fabricating a semiconductor device, in accordance with the present invention, includes the steps of providing a semiconductor wafer having exposed p-doped silicon regions and placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the exposed p-doped silicon regions to form an oxide on the exposed p-doped silicon regions when a potential difference is provided between the wafer and the solution.

Abstract: A system for measuring surface features having form birefringence in accordance with the present invention includes a radiation source for providing radiation incident on a surface having surface features. A radiation detecting device is provided for measuring characteristics of the incident radiation after being reflected from the surface features. A rotating stage rotates the surface such that incident light is directed at different angles due to the rotation of the rotating stage. A processor is included for processing the measured characteristics of the reflected light and correlating the characteristics to measure the surface features.