Abstract: The invention relates to a method for detection of analyte interaction with a channel molecule held in a membrane, comprising the optical detection of a modification in the flux of a signal molecule as it passes through the channel molecule by the action of a membrane potential, wherein the modification in the flux is caused by at least partial blockage of the channel molecule by the analyte. The invention further relates to bilayer arrays, components, methods of manufacture and use.

Abstract: The present invention relates to an exhaust hood (1) comprising a body (2) that is positioned above the cooker (O) such that there is a distance between the cooker (O) and the body (2), a projector (3) that is disposed on the body (2) and that can project onto the cooker (O) and/or the countertop (T) that surrounds the cooker (O) and whereon the cooker (O) is seated, a sensor (4) that is disposed on the body (2) and that can detect the movement in the area scanned, a virtual keyboard (5) that is projected by the projector (3), and a control unit (6) that is disposed on the body (2) and that performs operations by means of the virtual keyboard (5).

Abstract: An integrated circuit (300) includes a suspend circuit that includes a first input to receive a suspend signal, a first output to generate an awake signal, and outputs to provide control signals to various integrated circuit resources. During suspend mode, the suspend circuit suspends operation of the integrated circuit resources by driving its output pins to one of a plurality of predefined state selected by corresponding mode select signals and by locking its synchronous elements to known states. Upon termination of suspend mode, the circuit re-activates the integrated circuit resources according to a user-defined timing schedule. The user-defined timing schedule and the mode select signals may be provided to the integrated circuit during its configuration as part of a configuration bitstream.

Abstract: A method and apparatus to facilitate low-power consumption through a configurable suspend mode of operation of a PLD, the PLD comprising an application logic block coupled to receive configuration data bits and adapted to implement a logic application in response to the configuration data bits, a suspend pin coupled to receive a suspend signal, a write protect block coupled to the application logic block and adapted to prohibit the application logic block from changing logic states in response to a suspend mode initiated by the suspend signal; and an awake pin adapted to provide an awake signal that is indicative of a status of the suspend mode.

Abstract: A PLD (200) includes a power management unit (PMU 210) that selectively implements one or more different power-reduction techniques in response to power configuration signals (PC). By manipulating the PC signals, the PMU can independently enable/disable various supply voltage circuits (110, 120, 130) that power CLBs (101), IOBs (102), and configuration memory cells (106), can generate a capture signal that causes data stored in storage elements of the CLBs to be captured in configuration memory cells, and/or can switch power terminals of configuration memory cells between voltage supply circuits. Also, the PMU can sequentially apply and remove power from a number of configurable PLD portions in response to the PC signals, wherein each configurable portion may include any number of the PLD's resources.

Abstract: A GPS signal acquisition circuit includes a correlation engine, a decimator, a coherent integrator and an incoherent integrator. An over sampled GPS signal is fed into and processed by the correlation engine. The processed signal is sent to the decimator. The decimator generates an output for every M input from the correlation engine. When the decimated correlation engine output is processed in subsequent coherent and incoherent accumulations, the size of the memory required for high-sensitivity signal processing is greatly reduced. Therefore, the production cost can be lowered significantly.

Abstract: A configuration memory array for a programmable logic device includes an array of configuration memory cells arranged in rows and columns. Initially, each of the configuration memory cells is reset to a reset state. Each row of configuration memory cells is coupled to a corresponding data line and data line driver. During configuration, each data line driver drives a configuration data value having a first state or a second state onto the corresponding data line. A configuration data value having the first state has a polarity that tends to flip the reset state of a configuration memory cell. A repeater cell is connected to an intermediate location of each data line. Each repeater cell improves the drive of configuration data values having the first state.

Abstract: A searching apparatus comprises a searched object, a GPS transceiver and a communication unit. The GPS transceiver is arranged within the searched object and has an initializing circuit providing an enabling signal after receiving a control signal from the communication unit, a GPS receiver determining the position of the searched object when it is enabled by the initializing circuit, and an audio modulator converting the position data of the searched object into audio signal. The communication unit receives the audio signal and converts the audio signal to digital signal. The digital signal is displayed on monitor of computer or LCD panel to show the position of the searched object.

Abstract: A global positioning system comprises a receiving unit, a satellite positioning ASIC (application specific integrated circuit), and a digital interface circuit. The program memory and the micro controller in prior art global positioning system are advantageously replaced by a digital interface circuit. Therefore, the global positioning system of the present invention can achieve the advantages of miniature size, reduced cost and low electrical current consumption.