Patents by Inventor Oliver J. Kierse

Oliver J. Kierse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10730743
    Abstract: A gas sensor package is disclosed. The gas sensor package can include a housing defining a first chamber and a second chamber. An electrolyte can be provided in the first chamber. A gas inlet can provide fluid communication between the second chamber and the outside environs. The gas inlet can be configured to permit gas to enter the second chamber from the outside environs. An integrated device die can be mounted to the housing. The integrated device die can comprise a sensing element configured to detect the gas. The integrated device die can have a first side exposed to the first chamber and a second side exposed to the second chamber, with the first side opposite the second side.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: August 4, 2020
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Oliver J. Kierse, Rigan McGeehan, Alfonso Berduque, Donal Peter McAuliffe, Raymond J. Speer, Brendan Cawley, Brian J. Coffey, Gerald Blaney
  • Patent number: 10461151
    Abstract: An integrated circuit may include a semiconductor die having a trench formed in a surface of the semiconductor die. One or more circuit components may be formed on the surface of the semiconductor die. The trench can extend into the semiconductor die next to at least one circuit component. The trench may surround the circuit component partially or wholly. The trench may be filled with a material having a lower bulk modulus than the semiconductor die in which the trench is formed.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: October 29, 2019
    Assignee: Analog Devices Global
    Inventors: Patrick F. M. Poucher, Padraig L. Fitzgerald, John Jude O'Donnell, Oliver J. Kierse, Denis M. O'Connor
  • Publication number: 20190135614
    Abstract: A gas sensor package is disclosed. The gas sensor package can include a housing defining a first chamber and a second chamber. An electrolyte can be provided in the first chamber. A gas inlet can provide fluid communication between the second chamber and the outside environs. The gas inlet can be configured to permit gas to enter the second chamber from the outside environs. An integrated device die can be mounted to the housing. The integrated device die can comprise a sensing element configured to detect the gas. The integrated device die can have a first side exposed to the first chamber and a second side exposed to the second chamber, with the first side opposite the second side.
    Type: Application
    Filed: October 12, 2018
    Publication date: May 9, 2019
    Inventors: Oliver J. Kierse, Rigan McGeehan, Alfonso Berduque, Donal Peter McAuliffe, Raymond J. Speer, Brendan Cawley, Brian J. Coffey, Gerald Blaney
  • Patent number: 9786609
    Abstract: A stress shield for a plastic integrated circuit package is disclosed. A shield plate is attached by an adhesive to a top surface of an integrated circuit die such that the shield plate covers less than all of the top surface and leaves bond pads exposed. A molding material is applied over the shield plate and the integrated circuit die. The shield plate shields the integrated circuit die from stresses imparted by the molding material.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: October 10, 2017
    Assignee: ANALOG DEVICES GLOBAL
    Inventors: Oliver J Kierse, Frank Poucher, Michael J Cusack, Padraig L Fitzgerald, Patrick Elebert
  • Publication number: 20170257687
    Abstract: A three-dimensional printing technique can be used to form a microphone package. The microphone package can include a housing having a first side and a second side opposite the first side. A first electrical lead can be formed on an outer surface on the first side of the housing. A second electrical lead can be formed on an outer surface on the second side of the housing. The first electrical lead and the second electrical lead may be electrically shorted to one another. Further, vertical and horizontal conductors can be monolithically integrated within the housing.
    Type: Application
    Filed: May 19, 2017
    Publication date: September 7, 2017
    Inventors: Oliver J. Kierse, Christian Lillelund
  • Patent number: 9661408
    Abstract: A three-dimensional printing technique can be used to form a microphone package. The microphone package can include a housing having a first side and a second side opposite the first side. A first electrical lead can be formed on an outer surface on the first side of the housing. A second electrical lead can be formed on an outer surface on the second side of the housing. The first electrical lead and the second electrical lead may be electrically shorted to one another. Further, vertical and horizontal conductors can be monolithically integrated within the housing.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: May 23, 2017
    Assignee: ANALOG DEVICES, INC.
    Inventors: Oliver J. Kierse, Christian Lillelund
  • Publication number: 20170025497
    Abstract: An integrated circuit may include a semiconductor die having a trench formed in a surface of the semiconductor die. One or more circuit components may be formed on the surface of the semiconductor die. The trench can extend into the semiconductor die next to at least one circuit component. The trench may surround the circuit component partially or wholly. The trench may be filled with a material having a lower bulk modulus than the semiconductor die in which the trench is formed.
    Type: Application
    Filed: October 7, 2016
    Publication date: January 26, 2017
    Inventors: Patrick F.M. Poucher, Padraig L. Fitzgerald, John Jude O'Donnell, Oliver J. Kierse, Denis M. O'Connor
  • Patent number: 9466666
    Abstract: An integrated circuit may include a semiconductor die having a trench formed in a surface of the semiconductor die. One or more circuit components may be formed on the surface of the semiconductor die. The trench can extend into the semiconductor die next to at least one circuit component. The trench may surround the circuit component partially or wholly. The trench may be filled with a material having a lower bulk modulus than the semiconductor die in which the trench is formed.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: October 11, 2016
    Assignee: ANALOG DEVICES GLOBAL
    Inventors: Patrick F. M. Poucher, Padraig L. Fitzgerald, John Jude O'Donnell, Oliver J. Kierse, Denis M. O'Connor
  • Publication number: 20160105737
    Abstract: A three-dimensional printing technique can be used to form a microphone package. The microphone package can include a housing having a first side and a second side opposite the first side. A first electrical lead can be formed on an outer surface on the first side of the housing. A second electrical lead can be formed on an outer surface on the second side of the housing. The first electrical lead and the second electrical lead may be electrically shorted to one another. Further, vertical and horizontal conductors can be monolithically integrated within the housing.
    Type: Application
    Filed: October 9, 2015
    Publication date: April 14, 2016
    Inventors: Oliver J. Kierse, Christian Lillelund
  • Patent number: 9156680
    Abstract: A three-dimensional printing technique can be used to form a microphone package. The microphone package can include a housing having a first side and a second side opposite the first side. A first electrical lead can be formed on an outer surface on the first side of the housing. A second electrical lead can be formed on an outer surface on the second side of the housing. The first electrical lead and the second electrical lead may be electrically shorted to one another. Further, vertical and horizontal conductors can be monolithically integrated within the housing.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: October 13, 2015
    Assignee: ANALOG DEVICES, INC.
    Inventors: Oliver J. Kierse, Christian Lillelund
  • Publication number: 20150123256
    Abstract: A stress shield for a plastic integrated circuit package is disclosed. A shield plate is attached by an adhesive to a top surface of an integrated circuit die such that the shield plate covers less than all of the top surface and leaves bond pads exposed. A molding material is applied over the shield plate and the integrated circuit die. The shield plate shields the integrated circuit die from stresses imparted by the molding material.
    Type: Application
    Filed: November 5, 2013
    Publication date: May 7, 2015
    Applicant: Analog Devices Technology
    Inventors: Oliver J Kierse, Frank Poucher, Michael J. Cusack, Padraig L. Fitzgerald, Patrick Elebert
  • Patent number: 8890301
    Abstract: A packaged integrated device can include a die attach pad having a top surface and a bottom surface. A plurality of leads physically and electrically separated from the die attach pad can be positioned at least partially around the perimeter of the die attach pad. An integrated device die can be mounted on the top surface of the die attach pad. A package body can cover the integrated device die and at least part of the plurality of leads, and at least a portion of the bottom surface of each of the plurality of leads can be exposed through the package body. A plating layer can cover substantially the entire width of an etched lower portion of the outer end of each lead and at least the exposed portion of the bottom surface of each lead.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: November 18, 2014
    Assignee: Analog Devices, Inc.
    Inventor: Oliver J. Kierse
  • Publication number: 20140117473
    Abstract: A three-dimensional printing technique can be used to form a microphone package. The microphone package can include a housing having a first side and a second side opposite the first side. A first electrical lead can be formed on an outer surface on the first side of the housing. A second electrical lead can be formed on an outer surface on the second side of the housing. The first electrical lead and the second electrical lead may be electrically shorted to one another. Further, vertical and horizontal conductors can be monolithically integrated within the housing.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 1, 2014
    Applicant: ANALOG DEVICES, INC.
    Inventors: Oliver J. Kierse, Christian Lillelund
  • Publication number: 20140035113
    Abstract: A packaged integrated device can include a die attach pad having a top surface and a bottom surface. A plurality of leads physically and electrically separated from the die attach pad can be positioned at least partially around the perimeter of the die attach pad. An integrated device die can be mounted on the top surface of the die attach pad. A package body can cover the integrated device die and at least part of the plurality of leads, and at least a portion of the bottom surface of each of the plurality of leads can be exposed through the package body. A plating layer can cover substantially the entire width of an etched lower portion of the outer end of each lead and at least the exposed portion of the bottom surface of each lead.
    Type: Application
    Filed: August 1, 2012
    Publication date: February 6, 2014
    Applicant: ANALOG DEVICES, INC.
    Inventor: Oliver J. Kierse
  • Publication number: 20130292793
    Abstract: An integrated circuit may include a semiconductor die having a trench formed in a surface of the semiconductor die. One or more circuit components may be formed on the surface of the semiconductor die. The trench can extend into the semiconductor die next to at least one circuit component. The trench may surround the circuit component partially or wholly. The trench may be filled with a material having a lower bulk modulus than the semiconductor die in which the trench is formed.
    Type: Application
    Filed: January 14, 2013
    Publication date: November 7, 2013
    Applicant: ANALOG DEVICES TECHNOLOGY
    Inventors: Patrick F. M. POUCHER, Padraig L. FITZGERALD, John Jude O'DONNELL, Oliver J. KIERSE, Denis M. O'CONNOR
  • Patent number: 6225683
    Abstract: A “paddle-under-lead” (PUL) leadframe has the inner portions of an I.C. package's leads extend along the top of a paddle, to which they are affixed. An I.C. die is affixed to the top of the inner leads to form an I.C. package. Because the die is affixed directly to the leads, heat generated by the die is conducted out of the package via the package's leads, with the paddle serving as a heat spreader and heat sink. The leadframe's inner leads are affixed to the paddle, rather than separated from it as is done conventionally; this enables a larger die size to be accommodated within the same standard package size. A bifurcated inner lead design, usable with the PUL leadframe and others, divides the inner portions of an I.C. package's leads into laterally offset upper and lower sections, with the upper section serving as a wedge bond shelf and the lower section downset from the upper section.
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: May 1, 2001
    Assignee: Analog Devices, Inc.
    Inventors: Prasad V. V. Yalamanchili, Oliver J. Kierse
  • Patent number: 5796159
    Abstract: A leadframe that exhibits improved thermal dissipation and that can be incorporated in standard integrated circuit (IC) package designs is provided by extending the inner lead portions along a major surface of an IC, and attaching a heat sink on a side of the inner lead portions opposite the IC. The inner lead portions conduct heat from the IC to the heat sink, where it is dissipated into the moulding compound and radiated into the air. In the preferred embodiment, the leads have outer portions that are arranged on only two opposing sides of the IC package and comprise four sets of leads that initially intersect the IC along four lateral sides. This allows for a larger number of leads to contribute to heat dissipation. Added thermal dissipation is achieved by making the inner portion of a ground lead wider than the inner portion of any other lead.
    Type: Grant
    Filed: May 12, 1997
    Date of Patent: August 18, 1998
    Assignee: Analog Devices, Inc.
    Inventor: Oliver J. Kierse
  • Patent number: 5541446
    Abstract: A leadframe that exhibits improved thermal dissipation and that can be incorporated into standard integrated circuit (IC) packages is provided by widening the inner lead portions with respect to the outer lead portions and extending them along a major surface of the IC. In the preferred embodiment, the wide inner lead portions cover at least 80 percent of the IC surface and also support the IC, eliminating the need for a leadframe paddle. The wide inner lead portions are more efficient at conducting heat away from the IC than prior "standard" width inner lead portions because of the increased thermal contact area between them and the IC. Heat from the IC is conducted to the outside of the package via the leads and into the circuit board on which the IC package is mounted. Added thermal dissipation is achieved by making the inner portion of a ground lead wider than the inner portion of any other lead.
    Type: Grant
    Filed: September 26, 1995
    Date of Patent: July 30, 1996
    Assignee: Analog Devices, Inc.
    Inventor: Oliver J. Kierse
  • Patent number: 5486720
    Abstract: A package for housing integrated circuit chips that provides EMF shielding and thermal protection, while conforming to an industry recognized package outline, is provided. This EMF shielding and thermal protection is achieved by providing an electrically conductive heat sink that provides heat dissipation and that, together with a separate electrically conductive layer, also acts as an EMF shield. The heat sink contains a recess and is positioned against the conductive layer with the recess facing the conductive layer. The integrated circuit (IC) resides inside the cavity formed by the heat sink and conductive layer and is protected from EMF by the heat sink and conductive layer. The heat sink, electrically conductive layer and IC are then encapsulated in an electrically insulating molding compound that is molded to an industry recognized package outline. Additional ICs can be housed in this package by attaching them to the side of the electrically conductive layer opposite the heat sink.
    Type: Grant
    Filed: May 26, 1994
    Date of Patent: January 23, 1996
    Assignee: Analog Devices, Inc.
    Inventor: Oliver J. Kierse