Abstract: A method is provided, wherein a virtual internal master clock is used in connection with a RISC CPU. The RISC CPU comprises a number of concurrently operating function units, wherein each unit runs according to its own clocks, including multiple-stage totally unsynchronized clocks, in order to process a stream of instructions. The method includes the steps of generating a virtual model master clock having a clock cycle, and initializing each of the function units at the beginning of respectively corresponding processing cycles. The method further includes operating each function unit during a respectively corresponding processing cycle to carry out a task with respect to one of the instructions, in order to produce a result. Respective results are all evaluated in synchronization, by means of the master clock. This enables the instruction processing operation to be modeled using a sequential computer language, such as C or C++.

Abstract: Minimizing the effects of the requisite AGWN packets on transmission channel utilization without diminishing any of the aesthetic quality of the AGWN white noise on the voice or audio communication.

Abstract: Minimizing the effects of the requisite AGWN packets on transmission channel utilization without diminishing any of the aesthetic quality of the AGWN white noise on the voice or audio communication.

Abstract: A method, apparatus, and computer instructions for configuring routing devices in a network data processing system. A routing change is identified in the network data processing system. In response to the routing change being identified, a node topology is generated for a set of routing devices present in the network data processing system. A master network configuration table is built at a routing device within the set of routing devices. The network configuration table contains configuration data from the routing devices in the node topology. The master network configuration table is broadcast to the routing devices in the network data processing system.

Abstract: A system for controlling transmission of data over a network. In response to receiving a content request from a client device coupled to the network, an initial data packet is sent to the client device. In response to receiving a feedback packet from the client device, transmission of the content request is dynamically adjusted.

Abstract: An apparatus for a universal bundled connecting bus between computers and peripherals is presented. A bundled cable system includes a plurality of roller mechanisms for providing adjustable cables that connect peripheral devices to a computer. In one embodiment, the bundled cable system includes a separate internal cable for each communication link. Each of the internal cables includes a roller mechanism on each end that provides an adjustable cable for a user to vary in length in order to adequately connect peripheral devices to a computer. In another embodiment, the bundled cable system includes a single roller mechanism for each communication link. In this embodiment, each roller mechanism includes two adjustable cables that are extendible out from the roller mechanism, whereby one of the adjustable cables is extended and coupled to a peripheral device and the other adjustable cable is extended and coupled to a computing device.

Abstract: A system and method for programmable high precision quantization of analog variable is provided. A signal conversion circuit includes a digital switch subtractor, an ADC, and a counter/adder. During the ADC's first sampling stage, the digital switch subtractor activates a bypass switch that allows the ADC to sample an original analog input signal and generate a first digital value using the original analog input signal. During the ADC's second sampling stage, the digital switch subtractor configures resistor network switches based upon the first digital value, thereby creating a voltage drop across the resistor network when the original analog input signal is applied. As a result, the digital switch subtractor's output is a modified analog signal, which the ADC samples and generates a second digital value. The counter/adder combines the first digital value and the second digital value to produce a digital output that a computer system processes.