Abstract: Systems may include a broadband light source device, which may include at least one processor programmed or configured to receive an electrical control signal for operating a component of a plurality of components of a spectrum control device of the broadband light source device, determine which component of the plurality of components of the spectrum control device to operate based on the electrical control signal, and operate a first component of the plurality of components of the spectrum control device based on determining to operate the first component. Methods and computer program products are also disclosed.

Abstract: Methods and apparatuses relate to emulating architectural performance monitoring in a binary translation system. In one embodiment, a processor includes an architectural performance counter to maintain an architectural value associated with instruction execution, a register to store the architectural value of the architectural performance counter, binary translation logic to embed an architectural value from the architectural performance counter into a stream of translated instructions having a transactional code region and to store the architectural value into the register, and an execution unit to execute the transactional code region of the stream of translated instructions. The binary translation logic is configured to add the architectural value from the register to the architectural performance counter upon completion of the transactional code region of the stream of translated instructions.

Abstract: A multiple wavelength selective switch has an optics assembly to receive a first input optical signal from a first ingress port and a second input optical signal from a second ingress port. A switch assembly has a single switching mechanism to direct the first input optical signal to the optics assembly as a first output optical signal and the second input optical signal to the optics assembly as a second output optical signal. The switch assembly directs the first output optical signal to a first egress port selected from the first set of egress ports and directs the second output optical signal to a second egress port selected from the second set egress ports. The first egress port and the second egress port have the same wavelength channel. The multiple wavelength selective switch supports an arbitrary number of wavelength channels that can be switched at the same time. Each switch assembly directs signals from a set of ingress ports to a set of egress ports sharing the same wavelength channel.

Abstract: An apparatus and method for page level monitoring are described. For example, one embodiment of a method for monitoring memory pages comprises storing information related to each of a plurality of memory pages including an address identifying a location for a monitor variable for each of the plurality of memory pages in a data structure directly accessible only by a software layer operating at or above a first privilege level; detecting virtual-to-physical page mapping consistency changes or other page modifications to a particular memory page for which information is maintained in the data structure; responsively updating the monitor variable to reflect the consistency changes or page modifications; checking a first monitor variable associated with a first memory page prior to execution of first program code; and refraining from executing the first program code if the first monitor variable indicates consistency changes or page modifications to the first memory page.

Abstract: Methods and apparatuses relate to emulating architectural performance monitoring in a binary translation system. In one embodiment, a processor includes an architectural performance counter to maintain an architectural value associated with instruction execution, a register to store the architectural value of the architectural performance counter, binary translation logic to embed an architectural value from the architectural performance counter into a stream of translated instructions having a transactional code region and to store the architectural value into the register, and an execution unit to execute the transactional code region of the stream of translated instructions. The binary translation logic is configured to add the architectural value from the register to the architectural performance counter upon completion of the transactional code region of the stream of translated instructions.

Abstract: An apparatus and method for page level monitoring are described. For example, one embodiment of a method for monitoring memory pages comprises storing information related to each of a plurality of memory pages including an address identifying a location for a monitor variable for each of the plurality of memory pages in a data structure directly accessible only by a software layer operating at or above a first privilege level; detecting virtual-to-physical page mapping consistency changes or other page modifications to a particular memory page for which information is maintained in the data structure; responsively updating the monitor variable to reflect the consistency changes or page modifications; checking a first monitor variable associated with a first memory page prior to execution of first program code; and refraining from executing the first program code if the first monitor variable indicates consistency changes or page modifications to the first memory page.