Abstract: Synchronization apparatus in interconnected units of a data processing system resynchronize received bits from a bus with the internal clock of the unit. The synchronization arrangement has two identical synchonization devices which alternately process received strobe pulses which are used for sampling data bits into a first register, generating a gating pulse on one output and a validation pulse on a second output. In response to the gating pulse, bits stored in the first register are transferred to a second register to be available for use by processing logic in synchronism with the internal clock signal. The synchronization devices include two parallel synchronization circuits operating in opposite phase so that the detection of one strobe pulse by one circuit: automatically disables the other one.