Abstract: Test structures and a method for voltage contrast (VC) inspection are disclosed. In one embodiment, the test structure includes: a gate stack that is grounded by a ground to maintain the gate stack in an off state during VC inspection, which allows NFET defect detection using VC inspection prior to contact dielectric deposition. The test structure may alternatively include a gate stack that is biased by a bias to maintain the gate stack in an on state during VC inspection. The method may detect source-to-drain shorts in a transistor using VC inspection by providing a gate stack over a source and drain region of the transistor that is grounded by a ground to maintain the gate stack in an off state during VC inspection; and inspecting the transistor using voltage contrast. If the drain of the NFET brightens during VC inspection, this indicates a source to drain short.

Abstract: Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate.

Abstract: Structure and methods of determining the complete location of a buried short using voltage contrast inspection are disclosed. In one embodiment, a method includes providing a test structure having a PN junction thereunder; and using the PN junction to determine the location of the buried short using voltage contrast (VC) inspection. A test structure may include a plurality of test elements each having a PN junction thereunder, wherein a location of the buried short within the test structure can be determined using the PN junction and the VC inspection. The PN junction forces a change in illumination brightness of a test element including the buried short, thus allowing determination of the complete location of a buried short.

Abstract: A method for improving semiconductor yield by in-line repair of defects during manufacturing comprises inspecting dies on a wafer after a selected layer is formed on the dies, identifying defects in each of the dies, classifying the identified defects as killer or non-critical, for each killer defect determining an action to correct the defect, repairing the defect and returning the wafer to a next process step. Also disclosed is a method for determining an efficient repair process by dividing the die into a grid and using analysis of the grid to find a least invasive repair.

Abstract: A method and apparatus for identifying crystal defects in emitter-base junctions of NPN bipolar transistors uses a test structure having an NP junction that can be inspected using passive voltage contrast. The test structure eliminates the collector of the transistor and simulates only the emitter and base. Eliminating the collector removes an NP junction between collector and substrate of a wafer allowing charge to flow from the substrate to emitter if the emitter-base junction is defective since only one NP junction exists in the test structure. In one embodiment, the test structures are located between dies on a wafer and may be formed in groups of several thousand.

Abstract: A method for improving semiconductor yield by in-line repair of defects during manufacturing comprises inspecting dies on a wafer after a selected layer is formed on the dies, identifying defects in each of the dies, classifying the identified defects as killer or non-critical, for each killer defect determining an action to correct the defect, repairing the defect and returning the wafer to a next process step. Also disclosed is a method for determining an efficient repair process by dividing the die into a grid and using analysis of the grid to find a least invasive repair.

Abstract: Voltage contrast-based apparatuses, methods and systems for detection of continuity are described for use in evaluation of conducting components of a microcircuit such as a silicon wafer-based semiconductor chip. Two beams are directed to two separate conducting, electrically floating components on the sample, and are timed and delivered to be alternating pulses. One lower energy beam elicits its target to emit secondary electrons that are detected by an electron detector to produce an image. A second high-energy beam creates a virtual ground at its target. Voltage contrast images indicate whether there is continuity between the two conducting components.