Abstract: An anti-fuse system composed of a multiplicity of anti-fuse circuits (24, 26, 28, N) connected across a voltage source (10) by a pair of conductors (16, 18). Each anti-fuse circuit comprising an anti-fuse (30) connected in a series with a blow or control transistor (36) and a control circuit (44) for monitoring the status of the anti-fuse (30), Control circuit (44) provides an “on” signal to the gate (38) of control transistor (36) only when a_“select_” signal is received at an input (46) of control circuit (44) and if anti-fuse (30) has not been blown. After the anti-fuse (30) is blown, control circuit (44) turns off the control transistor (36) thereby providing a constant power source voltage across each anti-fuse circuit (24, 26, 28, N) regardless of the number of parallel anti-fuses which have been blown.

Abstract: A dynamic clamp is used in conjunction with capacitors with thinner dielectric or with deep trench capacitors to solve the problem of dielectric breakdown in high stress capacitors. The dynamic clamp is realized using a two stage pump operation cycle such that, during a first stage pump cycle, a middle node of a pair of series connected capacitors is pre-charged to a supply voltage and, during a second stage pump cycle, the middle node is coupled by a boost clock. Thus, at any moment in the pump operation cycle, the voltage across the capacitors is held within a safety range.

Abstract: An anti-fuse system composed of a multiplicity of anti-fuse circuits (24, 26, 28, N) connected across a voltage source (10) by a pair of conductors (16, 18). Each anti-fuse circuit comprising an anti-fuse (30) connected in series with a blow or control transistor (36) and a control circuit (44) for monitoring the status of the anti-fuse (30) at a voltage node (48) located between the anti-fuse (30) and blow transistor (36). When operating in a blow cycle, control circuit (44) provides an “on” signal to the gate (38) of blow transistor (36) only when a select signal is received at an input (46) of control circuit (44) and if anti-fuse (30) has not been blown. Therefore, after the anti-fuse (30) is blown, control circuit (44) turns off blow transistor (36) thereby providing a constant power source voltage across each anti-fuse circuit (24, 26, 28, N) regardless of the number of parallel anti-fuses which have been blown.

Abstract: A dynamic clamp is used in conjunction with capacitors with thinner dielectric or with deep trench capacitors to solve the problem of dielectric breakdown in high stress capacitors. The dynamic clamp is realized using a two stage pump operation cycle such that, during a first stage pump cycle, a middle node of a pair of series connected capacitors is pre-charged to a supply voltage and, during a second stage pump cycle, the middle node is coupled by a boost clock. Thus, at any moment in the pump operation cycle, the voltage across the capacitors is held within a safety range.

Abstract: In a controller for controlling a generator system on a memory chip, the controller operates as a state machine in accordance with a state diagram including a plurality of N states. A state storage device is responsive to input signals from a transition arrangement including a 1-out-of-N code indicating a change in the state diagram from a current state to a next state of the plurality of N states. The state storage device generates a revised plurality of N state output signals comprising a true State signal and a complementary true State signal for the next state of the plurality of N states. The state storage device is also responsive to an asynchronous Reset signal received from an external source for generating a Reset and a complementary Set output signal.

Abstract: A novel DRAM refresh method and system and a novel method of designing a low-power leakage monitoring device. With the DRAM refresh method, the time is adjusted based directly on the cell leakage condition. The method of designing a low-power leakage monitoring devices uses a memory cell identical to the cells in the real array. This monitor cell is designed so that it will represent the average cell or the worst cell leakage condition. If the leakage is severe, the refresh cycle time is significantly reduced, or halved. If the leakage level is very low or undetectable, then the refresh cycle time is significantly increased, or doubled. If the leakage is moderate, or in the normal range, the refresh time is optimized, so that the power consumption used for DRAM refresh is minimized.

Abstract: A novel DRAM refresh method and system and a novel method of designing a low-power leakage monitoring device. With the DRAM refresh method, the refresh cycle time is adjusted based directly on the cell leakage condition. The method of designing a low-power leakage monitoring devices uses a memory cell identical to the cells in the real array. This monitor cell is designed so that it will represent the average cell or the worst cell leakage condition. If the leakage is severe, the refresh cycle time is significantly reduced, or halved. If the leakage level is very low or undetectable, then the refresh cycle time is significantly increased, or doubled. If the leakage is moderate, or in the normal range, the refresh time is optimized, so that the power consumption used for DRAM refresh is minimized.

Abstract: A voltage converter circuit for an electronic device includes a transistor switch (140) for providing current pulses to a current input node. The transistor switch has a gate (128) and a turn-on threshold voltage. An adjustment circuit (114) provides a controlled voltage to the gate for turning on the transistor switch and the adjustment circuit includes a subcircuit for compensating for variations in the turn-on threshold voltage of the transistor switch. A timer (16) for enables the adjustment circuit for a preset period of time.

Abstract: Apparatus is used to dynamically control the power output of generators of a generator system on a chip to load circuits on the chip. A power bus is directed along at least one “spine” section on the chip which may intersect with at least one “arm” section on the chip for supplying power from the generators, which are coupled to the power bus in the “spine” section thereof, to circuits on the chip. The power bus has a feedback lead from each end which is remote from the generators for providing a continuous measurement of a voltage drop occurring at each remote end. At least one detector circuit is located at a predetermined point adjacent the generators of the chip for comparing a voltage from the generators measured at the predetermined point with the concurrent voltage drop measured at an associated remote end.

Abstract: A circuit for storing a bit of data is provided, where the circuit includes a first fuse having a first end and a second end and a second fuse having a third end and a fourth end. The first end of the first fuse is connected to a logic 0 input and its second end is connected to a common output. The third end of the second fuse is connected to a logic 1 input and the fourth end is connected to the common output. To store the bit of data, one of the first and second fuses is selectively blown. Hence, two fuses can be used to store a bit of information.

Abstract: A charge pump generator system and method is provided in which one or more charge pumps are operated at multiple charging rates depending upon the level reached by a voltage supply. The system includes a limiter which provides a control signal based upon the level of the voltage supply. The control signal selects the frequency of a multiple frequency oscillator coupled thereto. The selected frequency determines the charge transfer rate of a charge pump used to maintain the voltage supply.

Abstract: A voltage pump system for programming fuses on a semiconductor chip, in accordance with the present invention, includes a first pump system employing a supply voltage of the semiconductor chip as an input. The first pump system supplies an output voltage higher than the supply voltage on a first output line without raising the supply voltage of the semiconductor chip. A second pump system includes an input connected to the first output. The second pump system supplies an output voltage sufficient for programming electrical fuses on the semiconductor chip.

Abstract: A charge pump generator system and method is provided which more precisely maintains the level of an internally generated voltage supply by operating some or all of the available charge pumps depending upon the voltage level reached by the voltage supply. When the voltage supply is far from its target level, a first group and a second group of charge pumps are operated. The first group may preferably have a faster pumping rate or a greater number of charge pumps than the second group. When the voltage supply exceeds a first predetermined level, the first group of charge pumps is switched off while the second group remains on, such that the rate of charge transfer slows. The second group continues operating until a second, e.g. target, voltage level is exceeded. The slower rate of charge transfer then effective reduces overshoot, ringing and noise coupled onto the voltage supply line. Preferably, at least one charge pump operates in both standby and active modes, thereby reducing chip area.

Abstract: In a controller for controlling a generator system on a memory chip, the controller operates as a state machine in accordance with a state diagram including a plurality of X states. A state storage device is responsive to input signals indicating a change in the state diagram from a current state to a next state for generating a revised plurality of X state output signals comprising a true State signal and a complementary true State signal for the next state of the plurality of X states. An output arrangement is responsive to the true State signal and the complementary true State signal in the revised plurality of X state output signals from the state storage device for generating separate predetermined ones of M output signals associated with said next state for controlling the generator system while providing substantially zero current consumption when the state diagram reaches a final state of the plurality of X states.

Abstract: Improved transistor array device performance is obtained by use of bias voltage regulation which tracks with a fraction of a monitor transistor threshold voltage. The circuitry and methods are especially useful for improving the performance of transistor array devices such as DRAM and embedded DRAM. These benefits are obtained especially when at least two bias voltages normally supplied to the array are regulated by tracking with a fraction of an actual threshold voltage of at least one monitor transistor. Performance improvements include improved reliability, wider operational bias conditions, reduced power consumption and (in the case of memory cells) improved retention time.

Abstract: In a controller for controlling a generator system on a memory chip, the controller operates as a state machine in accordance with a state diagram including a plurality of X states. An evaluation arrangement evaluates a combination of only a predetermined one of a plurality of N input signals from remote devices, and only a predetermined one of a plurality of X state signals indicating a current state in the state diagram at any instant of time. The controller generates a plurality of Y output signals having a predetermined logical value that indicates that a change from one state to a next state in the state diagram is to be made when the predetermined one of both the plurality of N input signals and the plurality of X state signals comprise a predetermined logical value.

Abstract: In a flexible programmable controller for controlling a generator system on a memory chip, the controller operates as a state machine in accordance with a state diagram including a plurality of X states. A state storage device is responsive to input signals indicating a Reset state or a change in the state diagram from a current state to a next state for generating a Reset and an associated complementary Set signal or a revised plurality of X state output signals comprising a true State signal and a complementary true State signal for the next state of the plurality of X states. An output arrangement is responsive to the Reset and complementary Set signals or the true State signal and the complementary true State signal in the revised plurality of X state output signals from the state storage device for generating separate predetermined ones of M output signals associated with said Reset or next state for controlling the generator system.

Abstract: A plurality of voltage generating circuits forming a voltage generator system on a chip are controlled by a centralized voltage generator control arrangement. The voltage generator control arrangement includes a controller with a state machine (52) that receives control signals from various devices on the chip as, for example, a clock generator, voltage detectors, bondpads, testpads, fuses, and predetermined registers. From the received signals, the controller generates control signals to the plurality of generating circuits of the voltage generator system and other circuits on the chip in accordance with a predetermined program sequence for each phase of operation required by the generating circuits to provide the necessary stable voltages to circuits on the chip.

Abstract: A hearing aid has an input transducer, an amplifier and transmission circuit, an output transducer and a calculating unit working according to the principle of a neural structure. The calculating unit responds to a tap signal taken at the amplifier and transmission circuit and units an event signal that is supplied to the amplifier and transmission circuit and influences an output signal emitted thereby. At least the calculating unit is implemented in digital circuit technology. Such a hearing aid can be manufactured with little development and circuit outlay, works reliably and enables an optimum matching to the specific requirements of the hearing aid user.

Abstract: A hearing aid system with a hearing aid has a matching arrangement with a first memory for several parameter sets available for selection for each of several hearing situations, an input unit for selecting a current hearing situation and for selecting one of the several parameter sets available for this hearing situation, and a second memory for allocation data that identify the parameter sets selected for each hearing situation. For the determination of an optimal parameter set for each of several hearing situations, an optimal user-specific parameter set is allocated to each hearing situation as it arises during an optimization phase. After the optimization phase, the allocation data are evaluated for the determining an optimal parameter set for each hearing situation. This parameter set is then permanently programmed as the parameter set which will be called to set the transmission characteristics of the hearing aid whenever the hearing situation allocated thereto occurs.