Patents by Inventor Oliver Witnik

Oliver Witnik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230402555
    Abstract: A reflective semiconductor device includes an integrated circuit (IC) structure, and a pair of mirror elements over the IC structure. The pair of mirror elements are separated by a trench. Each mirror element includes a mirror layer of, for example, aluminum, on the IC structure, and a low temperature oxide (LTO) layer on the mirror layer. A high temperature oxide (HTO) layer is over the pair of mirror elements and fills the trench. A liquid crystal layer over the mirror elements provides a liquid crystal on semiconductor (LCOS) device. The two-oxide layer prevents mirror layer creep and/or agglomeration during formation of the HTO layer and provide a suitable surface for LCOS assembly without using specialized alloys.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Inventors: Thorsten E. Kammler, Robert Viktor Seidel, Michael Grillberger, Oliver Witnik, Nicole Brach, Raghav Shankar Uma Sankar
  • Patent number: 9171754
    Abstract: A method includes providing a semiconductor structure. The semiconductor structure includes a substrate having a frontside and a backside, an electrically conductive feature including copper provided at the frontside of the substrate and a low-k interlayer dielectric provided over the electrically conductive feature. A portion of the interlayer dielectric is etched. In the etch process, a surface of the electrically conductive feature is exposed. A degas process is performed, wherein the semiconductor structure is exposed to a first gas, and wherein the semiconductor structure is heated from the backside and from the frontside. A preclean process may be performed. The preclean process may include a first phase wherein the semiconductor structure is exposed to a substantially non-ionized second gas and a second phase wherein the semiconductor structure is exposed to a plasma created from the second gas.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Frank Koschinsky, Bernd Hintze, Oliver Witnik
  • Publication number: 20140349478
    Abstract: A method includes providing a semiconductor structure. The semiconductor structure includes a substrate having a frontside and a backside, an electrically conductive feature including copper provided at the frontside of the substrate and a low-k interlayer dielectric provided over the electrically conductive feature. A portion of the interlayer dielectric is etched. In the etch process, a surface of the electrically conductive feature is exposed. A degas process is performed, wherein the semiconductor structure is exposed to a first gas, and wherein the semiconductor structure is heated from the backside and from the frontside. A preclean process may be performed. The preclean process may include a first phase wherein the semiconductor structure is exposed to a substantially non-ionized second gas and a second phase wherein the semiconductor structure is exposed to a plasma created from the second gas.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 27, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Frank Koschinsky, Bernd Hintze, Oliver Witnik