Patents by Inventor Olivia Chen

Olivia Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Solder resist layer structures for terminating de-featured components and methods of making the same
    Patent number: 10658198
    Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Li-Sheng Weng, Chi-Te Chen, Wei-Lun Jen, Olivia Chen, Yun Ling
  • SOLDER RESIST LAYER STRUCTURES FOR TERMINATING DE-FEATURED COMPONENTS AND METHODS OF MAKING THE SAME
    Publication number: 20190181017
    Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.
    Type: Application
    Filed: February 4, 2019
    Publication date: June 13, 2019
    Applicant: INTEL CORPORATION
    Inventors: Li-Sheng Weng, Chi-Te Chen, Wei-Lun Jen, Olivia Chen, Yun Ling
  • Solder resist layer structures for terminating de-featured components and methods of making the same
    Patent number: 10244632
    Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Li-Sheng Weng, Chi-Te Chen, Wei-Lun Jen, Olivia Chen, Yun Ling
  • SOLDER RESIST LAYER STRUCTURES FOR TERMINATING DE-FEATURED COMPONENTS AND METHODS OF MAKING THE SAME
    Publication number: 20180255640
    Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.
    Type: Application
    Filed: March 2, 2017
    Publication date: September 6, 2018
    Applicant: INTEL CORPORATION
    Inventors: Li-Sheng Weng, Chi-Te Chen, Wei-Lun Jen, Olivia Chen, Yun Ling