Patents by Inventor Olivier Alavoine
Olivier Alavoine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240126438Abstract: This disclosure provides systems, methods, and devices for memory systems that support metadata. In a first aspect, a method of handling data and metadata at a memory device includes receiving data from the host via the at least one data connection into the first plurality of registers; receiving metadata from the host via the at least one non-data connection into the second plurality of registers; storing the data in the first portion of the memory array; and storing the metadata in the second portion of the memory array. Other aspects and features are also claimed and described.Type: ApplicationFiled: October 18, 2022Publication date: April 18, 2024Inventors: Jungwon Suh, Pankaj Sharadchandra Deshmukh, Michael Hawjing Lo, Subbarao Palacharla, Olivier Alavoine
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Publication number: 20230298682Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.Type: ApplicationFiled: May 24, 2023Publication date: September 21, 2023Inventors: Jungwon Suh, Dexter Tamio Chun, Anand Srinivasan, Olivier Alavoine, Laurent Rene Moll
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Patent number: 11728003Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.Type: GrantFiled: April 30, 2021Date of Patent: August 15, 2023Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Dexter Tamio Chun, Anand Srinivasan, Olivier Alavoine, Laurent Rene Moll
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Publication number: 20210358559Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.Type: ApplicationFiled: April 30, 2021Publication date: November 18, 2021Inventors: Jungwon Suh, Dexter Tamio Chun, Anand Srinivasan, Olivier Alavoine, Laurent Rene Moll
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Patent number: 11094393Abstract: Aspects of the present disclosure relate to systems and methods for issuing and executing a clear content command within a memory. Certain embodiments provide a method for the memory to receive a clear content command configured to clear content stored on the memory in a first set of memory cells of the plurality of memory cells of the plurality of memory banks. Certain embodiments provide a method of implementing within a DRAM memory the clear command by reusing existing refresh mechanism with minimal or no additional transistors or other hardware within the sense amplifier circuitry of the memory.Type: GrantFiled: September 2, 2020Date of Patent: August 17, 2021Assignee: QUALCOMM IncorporatedInventor: Olivier Alavoine
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Patent number: 10761774Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.Type: GrantFiled: April 3, 2018Date of Patent: September 1, 2020Assignee: Qualcomm IncorporatedInventors: Olivier Alavoine, Sejoong Lee, Tauseef Kazi, Simon Booth, Edoardo Regini, Renatas Jakushokas, Saurabh Patodia, Jeffrey Gemar, Michael Hawjing Lo, Vinod Chamarty, Boris Andreev, Tao Shen, Aravind Bhaskara, Wenbiao Wang, Stephen Molloy
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Publication number: 20180225066Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.Type: ApplicationFiled: April 3, 2018Publication date: August 9, 2018Inventors: Olivier Alavoine, Sejoong Lee, Tauseef Kazi, Simon Booth, Edoardo Regini, Renatas Jakushokas, Saurabh Patodia, Jeffrey Gemar, Michael Hawjing Lo, Vinod Chamarty, Boris Andreev, Tao Shen, Aravind Bhaskara, Wenbiao Wang, Stephen Molloy
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Patent number: 9965220Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.Type: GrantFiled: February 5, 2016Date of Patent: May 8, 2018Assignee: QUALCOMM IncorporatedInventors: Olivier Alavoine, Sejoong Lee, Tauseef Kazi, Simon Booth, Edoardo Regini, Renatas Jakushokas, Saurabh Patodia, Jeffrey Gemar, Haw-Jing Lo, Vinod Chamarty, Boris Andreev, Tao Shen, Aravind Bhaskara, Wenbiao Wang, Stephen Molloy
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Publication number: 20170228196Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.Type: ApplicationFiled: February 5, 2016Publication date: August 10, 2017Inventors: Olivier Alavoine, Sejoong Lee, Tauseef Kazi, Simon Booth, Edoardo Reginin, Renatas Jakushokas, Saurabh Patodia, Jeffery Gemar, Haw-Jing Lo, Vinod Chamarty, Boris Andreev, Tao Shen, Aravind Bhaskara, Wenbiao Wang, Stephen Molloy
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Patent number: 9703493Abstract: Systems, methods, and computer programs are disclosed for scheduling memory transactions. An embodiment of a method comprises determining future memory state data of a dynamic random access memory (DRAM) for a predetermined number of future clock cycles. The DRAM is electrically coupled to a system on chip (SoC). Based on the future memory state data, one of a plurality of pending memory transactions is selected that speculatively optimizes DRAM efficiency. The selected memory transaction is sent to a shared cache controller. If the selected memory transaction results in a cache miss, the selected memory transaction is sent to a DRAM controller.Type: GrantFiled: January 27, 2016Date of Patent: July 11, 2017Assignee: QUALCOMM IncorporatedInventor: Olivier Alavoine
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Publication number: 20170168727Abstract: Systems, methods, and computer programs are disclosed for scheduling memory transactions. An embodiment of a method comprises determining future memory state data of a dynamic random access memory (DRAM) for a predetermined number of future clock cycles. The DRAM is electrically coupled to a system on chip (SoC). Based on the future memory state data, one of a plurality of pending memory transactions is selected that speculatively optimizes DRAM efficiency. The selected memory transaction is sent to a shared cache controller. If the selected memory transaction results in a cache miss, the selected memory transaction is sent to a DRAM controller.Type: ApplicationFiled: January 27, 2016Publication date: June 15, 2017Inventor: OLIVIER ALAVOINE
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Patent number: 8452926Abstract: A digital system is provided with a memory interposer module configured to be coupled between a processor module and a memory module. The memory interposer module has a memory controller configured to couple to the memory module. It also includes a first memory emulator configured to couple to the processor module via a connector, wherein the first memory emulator is configured to emulate the memory module. There is an arbiter coupled between the memory controller and the memory emulator. A second memory emulator is connected to the arbiter, wherein the second memory emulator is also configured to emulate the memory module. Each memory emulator is operable to stall a memory request when a conflict occurs.Type: GrantFiled: January 5, 2010Date of Patent: May 28, 2013Assignee: Texas Instruments IncorporatedInventors: Philippe Gentric, Olivier Alavoine
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Publication number: 20110055490Abstract: A digital system is provided with a memory interposer module configured to be coupled between a processor module and a memory module. The memory interposer module has a memory controller configured to couple to the memory module. It also includes a first memory emulator configured to couple to the processor module via a connector, wherein the first memory emulator is configured to emulate the memory module. There is an arbiter coupled between the memory controller and the memory emulator. A second memory emulator is connected to the arbiter, wherein the second memory emulator is also configured to emulate the memory module. Each memory emulator is operable to stall a memory request when a conflict occurs.Type: ApplicationFiled: January 5, 2010Publication date: March 3, 2011Inventors: Philippe Gentric, Olivier Alavoine
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Patent number: 6237090Abstract: A primary circuit produces an internal resetting signal as a function of two input signals: an external resetting signal and a clock signal internal to the microprocessor. Depending on the characteristics of these two input signals, the internal resetting signal is generated according to a synchronous or an asynchronous mode. Generation of the internal resetting signal is delayed when the selection signal corresponds to the synchronous resetting mode.Type: GrantFiled: October 15, 1998Date of Patent: May 22, 2001Assignee: STMicroelectronics S.A.Inventor: Olivier Alavoine