Abstract: A process for protecting an upper stage of an electronic components against antenna effects includes providing a first structure having a first substrate with a first surface, a first stage of electronic components formed in a second surface of the first substrate, and a first stack having a last metallization level electrically connected to the second surface; and providing a second structure having a second substrate with a through-substrate via and having a second stage of electronic components having protective components that are arranged to drain electric charges to the second substrate. The process also includes joining the first and second structures so that the through-substrate via is electrically connected to the last metallization level of the first stack and forming a second stack on the second stage having a first metallization level electrically connected to the through-substrate via and to the first surface of the second substrate.

Abstract: A memory circuit includes a plurality of memory cells, each memory cell including a resistive memory element and a selection transistor of the FDSOI type connected in series with the resistive memory element. The selection transistor includes a channel region, a buried insulating layer, a back gate separated from the channel region by the buried insulating layer. The memory circuit further includes a circuit for biasing the back gate of the selection transistors, the biasing circuit being configured to apply a forward back-bias to the selection transistor of at least one memory cell during a programming or initialisation operation of the at least one memory cell.

Abstract: A data storage circuit includes an array of memory cells; a logic processing circuit configured to carry out a logic operation having N binary data as operands stored in N input memory cells, with N?2, the second input/output nodes of the input memory cells being linked by a common bit line, the logic processing circuit comprising: a transimpedance amplifier stage configured to supply an analogue read signal from the voltage of the common bit line; a comparator intended to compare the analogue read signal with a first adjustable reference voltage in order to generate a digital output signal corresponding to the result of the logic operation; a control unit configured to adjust the reference voltage to an amplitude selected from among N distinct predetermined amplitudes, depending on the type of logic operation.

Abstract: A data storage circuit includes a matrix of memory cells such that each memory cell comprises: a read circuit associated with at least one memory cell, comprising: a capacitive transimpedance amplifier stage configured to read a datum stored in a memory cell; the capacitive transimpedance amplifier stage comprising: an operational amplifier; a feedback capacitive impedance mounted between the output and the first input of the operational amplifier; a sequencer circuit configured to, following the reading of a datum corresponding to the second logic state, apply a control signal to the first input/output node having an amplitude lower than the first reference signal and maintain the selection transistor in an on state so as to replace, in the selected elementary storage component, a level of charges corresponding to the second logic state.

Abstract: A memory circuit includes a plurality of memory cells, each memory cell including a resistive memory element and a selection transistor of the FDSOI type connected in series with the resistive memory element. The selection transistor includes a channel region, a buried insulating layer, a back gate separated from the channel region by the buried insulating layer. The memory circuit further includes a circuit for biasing the back gate of the selection transistors, the biasing circuit being configured to apply a forward back-bias to the selection transistor of at least one memory cell during a programming or initialisation operation of the at least one memory cell.

Abstract: A process for protecting an upper stage of an electronic components against antenna effects includes providing a first structure having a first substrate with a first surface, a first stage of electronic components formed in a second surface of the first substrate, and a first stack having a last metallization level electrically connected to the second surface; and providing a second structure having a second substrate with a through-substrate via and having a second stage of electronic components having protective components that are arranged to drain electric charges to the second substrate. The process also includes joining the first and second structures so that the through-substrate via is electrically connected to the last metallization level of the first stack and forming a second stack on the second stage having a first metallization level electrically connected to the through-substrate via and to the first surface of the second substrate.

Abstract: A method of 3D circuit conception comprising: providing, to a circuit conception tool, circuit design files representing a 3D circuit design including one or more first circuit elements attributed to a first tier of the 3D circuit and one or more second circuit elements attributed to a second tier of the 3D circuit; modifying, by the circuit conception tool, a property of the one or more first and/or second circuit elements to permit any of the second circuit elements to superpose, or be superposed by, any of the first circuit elements; and performing, by the circuit conception tool, placement and routing of the 3D circuit design based on a 2D circuit representation, interconnection nodes of the one or more second circuit elements being defined in one or more interconnection levels of the 2D circuit representation.

Abstract: A method of generating, by a computing device, a 3D circuit layout based on a 2D circuit layout, the method comprising: assigning cells of first and second groups of circuit cells of the 2D circuit layout to first and second levels of the 3D circuit layout, the assignment of each circuit cell of the first and second groups being performed by: selecting, among at least one first row of a first level of the 3D circuit layout and at least one second row of a second level of the 3D circuit layout, the row having the greatest available space; and assigning the circuit cell to the selected row; and transmitting the 3D circuit layout to a manufacturing plant for fabrication.

Abstract: A method of 3D circuit conception comprising: providing, to a circuit conception tool, circuit design files representing a 3D circuit design including one or more first circuit elements attributed to a first tier of the 3D circuit and one or more second circuit elements attributed to a second tier of the 3D circuit; modifying, by the circuit conception tool, a property of the one or more first and/or second circuit elements to permit any of the second circuit elements to superpose, or be superposed by, any of the first circuit elements; and performing, by the circuit conception tool, placement and routing of the 3D circuit design based on a 2D circuit representation, interconnection nodes of the one or more second circuit elements being defined in one or more interconnection levels of the 2D circuit representation.

Abstract: A method of generating, by a computing device, a 3D circuit layout based on a 2D circuit layout, the method comprising: assigning cells of first and second groups of circuit cells of the 2D circuit layout to first and second levels of the 3D circuit layout, the assignment of each circuit cell of the first and second groups being performed by: selecting, among at least one first row of a first level of the 3D circuit layout and at least one second row of a second level of the 3D circuit layout, the row having the greatest available space; and assigning the circuit cell to the selected row; and transmitting the 3D circuit layout to a manufacturing plant for fabrication.

Abstract: The invention concerns a 3D circuit design method implemented by a processing device involving partitioning a 2D circuit representation into two or more tiers, the 2D circuit representation defining circuit elements interconnected by interconnecting wire each weighted based on at least one of: its length; its propagation delay; and its priority level, the 2D circuit representation initially forming a first tier, the partitioning involving: a) selecting a first highest ranking wire, interconnecting at least first and second circuit elements in the first tier; b) moving one of the first and second circuit elements connected by the selected wire to a further tier of the 3D circuit representation and replacing the interconnecting wire with a connecting via between the first and further tiers; and c) repeating a) and b) for one or more further interconnecting wires of the first tier.

Abstract: The invention concerns a 3D circuit design method implemented by a processing device involving partitioning a 2D circuit representation into two or more tiers, the 2D circuit representation defining circuit elements interconnected by interconnecting wire each weighted based on at least one of: its length; its propagation delay; and its priority level, the 2D circuit representation initially forming a first tier, the partitioning involving: a) selecting a first highest ranking wire, interconnecting at least first and second circuit elements in the first tier; b) moving one of the first and second circuit elements connected by the selected wire to a further tier of the 3D circuit representation and replacing the interconnecting wire with a connecting via between the first and further tiers; and c) repeating a) and b) for one or more further interconnecting wires of the first tier.

Abstract: A pixel with variable chromatic coordinates comprises a plurality of color sub-pixels consisting of a light emitter and a color filter. The light emitters are identical and have an emission spectrum that is able to be modulated according to their supply voltage and/or current. The pixel control circuit supplies each color sub-pixel with a supply voltage and/or current dependent on the color of the sub-pixel for its emission spectrum to approximate the transmission spectrum of the associated color filter. Control means enable the application time of the supply voltage and/or current to be modified according to the color of the sub-pixel to obtain a predetermined mean luminance during a predetermined period.

Abstract: An integrated circuit intended to be assembled with an electromagnetic radiation detector, the integrated circuit comprising a device for processing signals stemming from the detector, the processing device being covered with at least one conductive plate for protection against electromagnetic radiation, intended to be placed between said detector and said integrated circuit, said conductive plate including one or more apertures letting through conductive elements providing an electrical connection between the processing device and the detector.

Abstract: Improved method to fabricate a microelectronic device provided with at least one circuit to detect biological elements, comprising the steps of: a) forming transistors, depositing at least one layer in at least one insulating material (141) coating said transistors, forming one or more holes (143) in said layer of insulating material (141), so as to expose the upper face of the respective gate (135) of first-type transistors, filling the holes with a gate material, b) removing, at least in part, the respective gate (135) of the first-type transistors, whilst the gate of second-type transistors is protected, the method prior to or at the same time as said removal conducted at step b) further comprising the removal of said gate material.

Abstract: A pixel with variable chromatic coordinates comprises a plurality of color sub-pixels consisting of a light emitter and a color filter. The light emitters are identical and have an emission spectrum that is able to be modulated according to their supply voltage and/or current. The pixel control circuit supplies each color sub-pixel with a supply voltage and/or current dependent on the color of the sub-pixel for its emission spectrum to approximate the transmission spectrum of the associated color filter. Control means enable the application time of the supply voltage and/or current to be modified according to the color of the sub-pixel to obtain a predetermined mean luminance during a predetermined period.

Abstract: Improved method to fabricate a microelectronic device provided with at least one circuit to detect biological elements, comprising the steps of: a) forming transistors, depositing at least one layer in at least one insulating material (141) coating said transistors, forming one or more holes (143) in said layer of insulating material (141), so as to expose the upper face of the respective gate (135) of first-type transistors, filling the holes with a gate material, b) removing, at least in part, the respective gate (135) of the first-type transistors, whilst the gate of second-type transistors is protected, the method prior to or at the same time as said removal conducted at step b) further comprising the removal of said gate material.

Abstract: The particle detection circuit comprises a plurality of basic circuits. Each basic circuit comprises a particle detector element connected to an associated counter and a summing circuit having a first input connected to the output of the counter. Basic circuits, each forming a subpixel, are grouped together by series connection of their summing circuits to form a pixel. The output of the pixel, formed by the output of the summing circuit of a last basic circuit of the pixel, supplies counting signals representative of the number of particles detected by the set of basic circuits of the pixel. Disabling certain basic circuits of the pixel, by selective zero resetting of the first input of their summing circuit, can enable only the particles detected by certain zones of the pixel to be counted.

Abstract: An integrated circuit intended to be assembled with an electromagnetic radiation detector, the integrated circuit comprising a device for processing signals stemming from the detector, the processing device being covered with at least one conductive plate for protection against electromagnetic radiation, intended to be placed between said detector and said integrated circuit, said conductive plate including one or more apertures letting through conductive elements providing an electrical connection between the processing device and the detector.

Abstract: The particle detection circuit comprises a plurality of basic circuits. Each basic circuit comprises a particle detector element connected to an associated counter and a summing circuit having a first input connected to the output of the counter. Basic circuits, each forming a subpixel, are grouped together by series connection of their summing circuits to form a pixel. The output of the pixel, formed by the output of the summing circuit of a last basic circuit of the pixel, supplies counting signals representative of the number of particles detected by the set of basic circuits of the pixel. Disabling certain basic circuits of the pixel, by selective zero resetting of the first input of their summing circuit, can enable only the particles detected by certain zones of the pixel to be counted.