Abstract: Disclosed are novel methods and apparatus for efficiently providing instruction-based BIST of memory interconnects. In an embodiment of the present invention, a method of testing a memory interconnect between an external memory module and a chip is disclosed. The method includes: providing an on-chip memory controller coupled to the external memory module, the on-chip memory controller sending and receiving data to and from the external memory module; providing an on-chip built-in self-test (BIST) module coupled to the on-chip memory controller, the BIST module including an instruction register to store a plurality of instructions; testing the external memory module; and once the external memory module has successfully passed the testing, utilizing the external memory module in testing the memory interconnect.

Abstract: A method generates and verifies a design-for-test (DFT) library for an automatic test pattern generator (ATPG) tool. The method includes (a) creating a synthesis library including primitives to be used to create the modules, the primitives being the same as primitives used by the ATPG tool, (b) creating a register transfer level (RTL) description for each module, (c) performing synthesis using the synthesis library and the RTL description to create a gate level description for each module, and (d) generating the DFT library by converting a hardware description language (HDL) of the gate level description into a script language for the ATPG tool to create a DFT file for each module. The method may further include (e) converting the DFT files into a RTL description to create a pseudo-RTL description for each module, and (f) comparing the RTL description and the pseudo-RTL description for verification of the DFT library.

Abstract: Disclosed are novel methods and apparatus for efficiently providing concurrently programmable dynamic memory built-in self-testing (BIST). In an embodiment of the present invention, a method of utilizing a BIST system is disclosed. The method includes: loading setup data into a configuration register; loading a first instruction into a shift register; loading the first instruction into an update register; executing the loaded first instruction to perform a memory test; upon receiving a first update command, loading a second instruction into the shift register; and upon receiving a second update command, loading the second instruction into the update register.

Abstract: Disclosed are novel methods and apparatus for efficiently providing instruction-based BIST of external memory. In an embodiment, a built-in self-testing system is disclosed. The system includes an external memory module, an on-chip memory controller coupled to the external memory module, an on-chip built-in self-test (BIST) module coupled to the on-chip memory controller, and an interface controller coupled to the BIST module to provide an interface to access the BIST module. The on-chip memory controller may send and receive data to and from the external memory module. And, the BIST module may include an instruction register to store a plurality of instructions.

Abstract: A method generates a test pattern for an integrated circuit (IC) design using a functional verification program. The functional verification program includes a stimulus generator, an expected-response generator, and an interface defining ports of the IC design. The method includes (a) converting input ports in the interface into bi-directional in/out ports, (b) supplying stimuli to the converted in/out ports and original in/out ports in the interface by executing the stimulus generator, (c) sampling the stimuli supplied to the converted in/out ports and the original in/out ports, and (d) recording the sampled stimuli. The method may further include (e) creating bi-directional shadow ports in the interface, the shadow ports corresponding to the in/out ports and output ports of the IC design, (f) supplying expected responses to the shadow ports by executing the expected-response generator, (g) sampling the expected responses from the shadow ports, and (h) recording the sampled expected response.

Abstract: The invention relates to an integrated bus signal hold cell that is coupled with a bus line via a common input/output, and that has at least two inverters for holding the last state of the bus line. The outputs of the inverters are coupled with each other's inputs, respectively. The input of the first inverter is coupled with the input/output. The output of the second inverter is coupled with the input/output. An additional input is provided via which the bus signal hold cell can be charged with a defined test signal. The invention also relates to an integrated bus system and a method for driving a bus signal hold cell and a bus system.

Abstract: Disclosed are novel methods and apparatus for efficiently providing concurrently programmable dynamic memory built-in self-testing (BIST). In an embodiment of the present invention, a method of utilizing a BIST system is disclosed. The method includes: loading setup data into a configuration register; loading a first instruction into a shift register; loading the first instruction into an update register; executing the loaded first instruction to perform a memory test; upon receiving a first update command, loading a second instruction into the shift register; and upon receiving a second update command, loading the second instruction into the update register.

Abstract: A method generates and verifies a design-for-test (DFT) library for an automatic test pattern generator (ATPG) tool. The method includes (a) creating a synthesis library including primitives to be used to create the modules, the primitives being the same as primitives used by the ATPG tool, (b) creating a register transfer level (RTL) description for each module, (c) performing synthesis using the synthesis library and the RTL description to create a gate level description for each module, and (d) generating the DFT library by converting a hardware description language (HDL) of the gate level description into a script language for the ATPG tool to create a DFT file for each module. The method may further include (e) converting the DFT files into a RTL description to create a pseudo-RTL description for each module, and (f) comparing the RTL description and the pseudo-RTL description for verification of the DFT library.

Abstract: A method generates a test pattern for an integrated circuit (IC) design using a functional verification program. The functional verification program includes a stimulus generator, an expected-response generator, and an interface defining ports of the IC design. The method includes (a) converting input ports in the interface into bi-directional in/out ports, (b) supplying stimuli to the converted in/out ports and original in/out ports in the interface by executing the stimulus generator, (c) sampling the stimuli supplied to the converted in/out ports and the original in/out ports, and (d) recording the sampled stimuli. The method may further include (e) creating bi-directional shadow ports in the interface, the shadow ports corresponding to the in/out ports and output ports of the IC design, (f) supplying expected responses to the shadow ports by executing the expected-response generator, (g) sampling the expected responses from the shadow ports, and (h) recording the sampled expected response.

Abstract: Disclosed are novel methods and apparatus for efficiently providing instruction-based BIST of memory interconnects. In an embodiment of the present invention, a method of testing a memory interconnect between an external memory module and a chip is disclosed. The method includes: providing an on-chip memory controller coupled to the external memory module, the on-chip memory controller sending and receiving data to and from the external memory module; providing an on-chip built-in self-test (BIST) module coupled to the on-chip memory controller, the BIST module including an instruction register to store a plurality of instructions; testing the external memory module; and once the external memory module has successfully passed the testing, utilizing the external memory module in testing the memory interconnect.

Abstract: Disclosed are novel methods and apparatus for efficiently providing instruction-based BIST of external memory. In an embodiment, a built-in self-testing system is disclosed. The system includes an external memory module, an on-chip memory controller coupled to the external memory module, an on-chip built-in self-test (BIST) module coupled to the on-chip memory controller, and an interface controller coupled to the BIST module to provide an interface to access the BIST module. The on-chip memory controller may send and receive data to and from the external memory module. And, the BIST module may include an instruction register to store a plurality of instructions.

Abstract: The invention relates to an integrated bus signal hold cell that is coupled with a bus line via a common input/output, and that has at least two inverters for holding the last state of the bus line. The outputs of the inverters are coupled with each other's inputs, respectively. The input of the first inverter is coupled with the input/output. The output of the second inverter is coupled with the input/output. An additional input is provided via which the bus signal hold cell can be charged with a defined test signal. The invention also relates to an integrated bus system and a method for driving a bus signal hold cell and a bus system.