Abstract: The present invention relates to a microprocessor including an operator dedicated to a concatenation of variable-length codes to form a sequence of contiguous codes, the operator being associated with a dedicated instruction using two parameters, a first one of which is a word containing a group of bits and the second one of which indicates the length of the group of bits, the operator responding to the dedicated instruction by isolating, in the first parameter, the group of bits having the length indicated by the second parameter and by inserting the bit group so isolated into an active register, in concatenation with a bit group which has been inserted in the active register by a previous execution of the dedicated instruction.

Abstract: The present invention relates to a microprocessor including an operator dedicated to a signature calculation over a bit sequence, the operator being associated with a dedicated instruction using two parameters, a first one of which is a word including a group of bits forming a successive portion of the sequence, and the second parameter of which indicates the length of the group of bits, the operator responding to the dedicated instruction by updating a signature register with a signature calculated over the content of the signature register and over the group of bits.