Patents by Inventor Olivier Doaré

Olivier Doaré has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11320526
    Abstract: A communication unit (300) is described that includes a plurality of cascaded devices that includes at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device comprises a modulator circuit (362) configured to: receive a system clock signal and a frame start signal; modulate the system clock signal with the frame start signal to produce a modulated master-slave clock signal (384); and transmit the modulated master-slave clock signal (384) to the at least one slave device. The at least one slave device comprises a demodulator circuit (364) configured to: receive and demodulate the modulated master-slave clock signal (384); and re-create therefrom the system clock signal (388, 385) and the frame start signal (390, 386).
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: May 3, 2022
    Assignee: NXP USA, Inc.
    Inventors: Didier Salle, Cristian Pavao Moreira, Dominique Delbecq, Olivier Doaré, Jean-Stephane Vigier, Birama Goumballa
  • Patent number: 11054513
    Abstract: A communication unit (700) is described that includes a plurality of cascaded devices that comprise at least one master device (710) and at least one slave device (720, 723) configured in a master-slave arrangement. The at least one master device (710) and at least one slave device (720, 723) each comprise: an analog-to-digital converter, ADC, (741, 742) configured to use a same re-created system clock signal (788, 790) to align respective sampling instants between each ADC (741, 742). The at least one master device (710) comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit (708), configured to output a system clock signal (782, 784); and a modulator circuit (762) coupled to the clock generation circuit and configured to receive and distribute the system clock signal (784).
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: July 6, 2021
    Assignee: NXP USA, INC.
    Inventors: Olivier Doaré, Didier Salle, Cristian Pavao Moreira, Julien Orlando, Jean-Stephane Vigier, Andres Barrilado Gonzalez
  • Patent number: 10648870
    Abstract: Disclosed is a temperature sensor including a first current generator configured to generate a proportional to absolute temperature (PTAT) current, a second current generator configured to generate an inverse PTAT (IPTAT) current, the PTAT current and IPTAT current being combined to form a reference current having a sensitivity relative to temperature, a plurality of current mirrors to adjust the sensitivity and gain of the reference current, and a variable resistor to set an output calibration voltage based on the generated current.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: May 12, 2020
    Assignee: NXP USA, Inc.
    Inventors: Birama Goumballa, Didier Salle, Olivier Doare, Cristian Pavao Moreira
  • Publication number: 20200003882
    Abstract: A communication unit (300) is described that includes a plurality of cascaded devices that includes at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device comprises a modulator circuit (362) configured to: receive a system clock signal and a frame start signal; modulate the system clock signal with the frame start signal to produce a modulated master-slave clock signal (384); and transmit the modulated master-slave clock signal (384) to the at least one slave device. The at least one slave device comprises a demodulator circuit (364) configured to: receive and demodulate the modulated master-slave clock signal (384); and re-create therefrom the system clock signal (388, 385) and the frame start signal (390, 386).
    Type: Application
    Filed: June 20, 2019
    Publication date: January 2, 2020
    Inventors: Didier Salle, Cristian Pavao Moreira, Dominique Delbecq, Olivier Doaré, Jean-Stephane Vigier, Birama Goumballa
  • Publication number: 20200003862
    Abstract: A communication unit (900) includes a plurality of cascaded devices that comprise at least one master device (910) and at least one slave device (920, 923) configured in a master-slave arrangement. The at least one master device (910) and at least one slave device (920, 923) each include: a demodulator circuit (964, 965) configured to receive a distributed reference clock signal (984) and re-create a system clock signal (988, 990) therefrom; a clock generation circuit comprising an internally-generated reference phase locked loop configured to receive the re-created system clock signal (988, 990) to create a master-slave clock signal; and an analog-to-digital converter, ADC, (941, 942) coupled to the reference phase locked loop and configured to use a same master-slave clock signal (988, 990) to align respective sampling instants between each ADC (941, 942) of the at least one master device (910) and at least one slave device (920, 923).
    Type: Application
    Filed: June 21, 2019
    Publication date: January 2, 2020
    Inventors: Olivier Doaré, Didier Salle, Cristian Pavao Moreira, Julien Orlando, Jean-Stephane Vigier, Andres Barrilado Gonzalez
  • Publication number: 20200003883
    Abstract: A communication unit (700) is described that includes a plurality of cascaded devices that comprise at least one master device (710) and at least one slave device (720, 723) configured in a master-slave arrangement. The at least one master device (710) and at least one slave device (720, 723) each comprise: an analog-to-digital converter, ADC, (741, 742) configured to use a same re-created system clock signal (788, 790) to align respective sampling instants between each ADC (741, 742). The at least one master device (710) comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit (708), configured to output a system clock signal (782, 784); and a modulator circuit (762) coupled to the clock generation circuit and configured to receive and distribute the system clock signal (784).
    Type: Application
    Filed: June 21, 2019
    Publication date: January 2, 2020
    Inventors: Olivier Doaré, Didier Salle, Cristian Pavao Moreira, Julien Orlando, Jean-Stephane Vigier, Andres Barrilado Gonzalez
  • Patent number: 10250213
    Abstract: A calibration circuit and a method for calibrating a RC circuit, such as a high-pass filter, of an integrated circuit are provided. The calibration circuit comprises a filter arrangement having tuneable filter for filtering an input signal having a predetermined frequency. The filter comprises tuneable resistor elements, a saturation detector for detecting saturation and non-saturation of the tuneable filter by comparing a comparison voltage with the signal voltage of the filtered input signal, calibration control logic for providing incrementing and decrementing counter signals.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: April 2, 2019
    Assignee: NXP USA, Inx.
    Inventors: Cristian Pavao-Moreira, Olivier Doare, Birama Goumballa
  • Patent number: 9897975
    Abstract: Various embodiments include a time to digital converter device comprising: a medium resolution delay unit including a plurality of buffers, the medium resolution delay unit configured to receive as inputs a reference clock signal and a data clock signal and configured to output a plurality of delayed data clock signals wherein the delay between the plurality of delayed data clock signal is a medium resolution delay value; a fine resolution delay unit including a plurality of cores configured to receive as inputs the reference clock signal and the plurality of delayed data clock signals from the medium resolution delay unit, wherein the plurality of cores includes: a first bank of delays configured to receive one of the plurality of the delayed data clock signals, a second bank of delays configured to receive the reference clock signal, and; and a fast flip flop connected to the outputs of the first bank of delays and the second bank of delays, wherein the output of the fast flip flop is used to check the phas
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: February 20, 2018
    Assignee: NXP USA, INC.
    Inventors: Didier Salle, Olivier Doare, Cristian Pavao Moreira, Birama Goumballa
  • Patent number: 9835715
    Abstract: An integrated circuit for a radar device comprises at least one transmitter and at least one receiver. The integrated circuit comprises: a direct digital synthesizer, DDS, configured to output a control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS. In a first mode of operation, the DDS and multiplier cooperate to generate at least one transmitter signal to be transmitted from the radar device; and in a second mode of operation the DDS and multiplier cooperate to generate at least one low frequency modulated transmitter signal to be internally routed to the at least one receiver for calibrating the at least one receiver.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: December 5, 2017
    Assignee: NXP USA, Inc.
    Inventors: Dominique Delbecq, Olivier Doare, Gilles Montoriol
  • Publication number: 20170307451
    Abstract: Disclosed is a temperature sensor including a first current generator configured to generate a proportional to absolute temperature (PTAT) current, a second current generator configured to generate an inverse PTAT (IPTAT) current, the PTAT current and IPTAT current being combined to form a reference current having a sensitivity relative to temperature, a plurality of current mirrors to adjust the sensitivity and gain of the reference current, and a variable resistor to set an output calibration voltage based on the generated current.
    Type: Application
    Filed: March 20, 2017
    Publication date: October 26, 2017
    Inventors: Birama GOUMBALLA, Didier SALLE, Olivier DOARE, Cristian Pavao Moreira
  • Publication number: 20170293265
    Abstract: Various embodiments include a time to digital converter device comprising: a medium resolution delay unit including a plurality of buffers, the medium resolution delay unit configured to receive as inputs a reference clock signal and a data clock signal and configured to output a plurality of delayed data clock signals wherein the delay between the plurality of delayed data clock signal is a medium resolution delay value; a fine resolution delay unit including a plurality of cores configured to receive as inputs the reference clock signal and the plurality of delayed data clock signals from the medium resolution delay unit, wherein the plurality of cores includes: a first bank of delays configured to receive one of the plurality of the delayed data clock signals, a second bank of delays configured to receive the reference clock signal, and; and a fast flip flop connected to the outputs of the first bank of delays and the second bank of delays, wherein the output of the fast flip flop is used to check the phas
    Type: Application
    Filed: April 3, 2017
    Publication date: October 12, 2017
    Inventors: Didier Salle, Olivier Doare, Cristian Pavao Moreira, Birama Goumballa
  • Patent number: 9720074
    Abstract: A circuitry for and a method of generating a frequency modulated radar transmitter signal are provided. The circuitry comprises a modulation signal generator for generating a modulation signal having a waveform describing a required frequency modulation of the frequency modulated radar transmitter signal and comprises a PLL circuitry for generating the frequency modulated radar transmitter signal in dependence of the modulation signal. In the PLL circuitry a controllable frequency divider controls the output frequency of the PLL circuitry in dependence of the modulation signal. The PLL circuitry further comprises a phase detector, a controllable oscillator and possibly a low pass filter. The PLL circuitry further comprises a calibration circuitry being configured to control a parameter of at least one of the phase detector and the controllable oscillator to maintain a loop gain of PLL circuitry.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: August 1, 2017
    Assignee: NXP USA, Inc.
    Inventors: Didier Salle, Olivier Doare, Christophe Landez
  • Patent number: 9722648
    Abstract: An integrated circuit comprises a frequency detector. The frequency detector comprises a timer state machine unit operably couplable to a timer and arranged to receive an incoming carrier signal; determine whether the incoming carrier signal comprises a valid frequency; generate a valid carrier indication when the incoming carrier signal is determined as having a valid frequency; and adjust the timer between at least a first timing mode of operation and a second timing mode of operation of the frequency detector in response to the determination.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: August 1, 2017
    Assignee: NXP USA, Inc.
    Inventors: Philippe Freitas, Olivier Doare, Valerie Escarpit, Christophe Landez, Xavier Lhuillier
  • Publication number: 20160233846
    Abstract: A calibration circuit and a method for calibrating a RC circuit, such as a high-pass filter, of an integrated circuit are provided. The calibration circuit comprises a filter arrangement having tuneable filter for filtering an input signal having a predetermined frequency. The filter comprises tuneable resistor elements, a saturation detector for detecting saturation and non-saturation of the tuneable filter by comparing a comparison voltage with the signal voltage of the filtered input signal, calibration control logic for providing incrementing and decrementing counter signals.
    Type: Application
    Filed: September 27, 2013
    Publication date: August 11, 2016
    Inventors: Cristian PAVAO-MOREIRA, Olivier DOARE, Birama GOUMBALLA
  • Publication number: 20160109559
    Abstract: An integrated circuit for a radar device comprises at least one transmitter and at least one receiver. The integrated circuit comprises: a direct digital synthesiser, DDS, configured to output a control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS. In a first mode of operation, the DDS and multiplier cooperate to generate at least one transmitter signal to be transmitted from the radar device; and in a second mode of operation the DDS and multiplier cooperate to generate at least one low frequency modulated transmitter signal to be internally routed to the at least one receiver for calibrating the at least one receiver.
    Type: Application
    Filed: March 17, 2015
    Publication date: April 21, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: DOMINIQUE DELBECQ, OLIVIER DOARE, GILLES MONTORIOL
  • Patent number: 9197394
    Abstract: Versatility and flexibility of integrated circuits can be accomplished by remote control via a serial interface, such as SPI. Read/write accesses to the SPI slave node can be achieved according to SPI protocol by the master node. Additionally, a state machine associated to the slave node SPI needs a local clock to exercise the control of the analog functions following a write access. The serial protocol defines a serial data word transfer to comprise a number of reserved clock cycles that are not assigned for communicating a data bit value of the data word. The slave device comprises a clock unit coupled to the serial clock line for providing a derived clock based on reserved clock cycles. The derived clock is used internally in the slave device to perform internal synchronous operations.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: November 24, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Olivier Doare, Christophe Landez
  • Publication number: 20150219753
    Abstract: A circuitry for and a method of generating a frequency modulated radar transmitter signal are provided. The circuitry comprises a modulation signal generator for generating a modulation signal having a waveform describing a required frequency modulation of the frequency modulated radar transmitter signal and comprises a PLL circuitry for generating the frequency modulated radar transmitter signal in dependence of the modulation signal. In the PLL circuitry a controllable frequency divider controls the output frequency of the PLL circuitry in dependence of the modulation signal. The PLL circuitry further comprises a phase detector, a controllable oscillator and possibly a low pass filter. The PLL circuitry further comprises a calibration circuitry being configured to control a parameter of at least one of the phase detector and the controllable oscillator to maintain a loop gain of PLL circuitry.
    Type: Application
    Filed: July 7, 2014
    Publication date: August 6, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: DIDIER SALLE, OLIVIER DOARE, CHRISTOPHE LANDEZ
  • Publication number: 20150163046
    Abstract: Versatility and flexibility of integrated circuits can be accomplished by remote control via a serial interface, such as SPI. Read/write accesses to the SPI slave node can be achieved according to SPI protocol by the master node. Additionally, a state machine associated to the slave node SPI needs a local clock to exercise the control of the analog functions following a write access. The serial protocol defines a serial data word transfer to comprise a number of reserved clock cycles that are not assigned for communicating a data bit value of the data word. The slave device comprises a clock unit coupled to the serial clock line for providing a derived clock based on reserved clock cycles. The derived clock is used internally in the slave device to perform internal synchronous operations.
    Type: Application
    Filed: May 29, 2012
    Publication date: June 11, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Olivier Doare, Christophe Landez
  • Patent number: 8731502
    Abstract: An integrated circuit comprises frequency generation circuitry for controlling a frequency source for use in an automotive radar system. The frequency generation circuitry comprises low-path modulation circuitry arranged to generate a first, low-path control signal for providing lower frequency modulation of the frequency source, the low-path modulation circuitry comprising a Phase Locked Loop (PLL) arranged to generate the low-path control signal for controlling the frequency source and a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control module operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of at least a first, lower frequency pattern control signal. The frequency generation circuitry further comprises high-path modulation circuitry arranged to generate a second, high-path control signal for providing higher frequency modulation of the frequency source.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: May 20, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Didier Salle, Olivier Doare, Stephane Dugalleix
  • Publication number: 20130331050
    Abstract: An integrated circuit comprises a frequency detector. The frequency detector comprises a timer state machine unit operably couplable to a timer and arranged to receive an incoming carrier signal; determine whether the incoming carrier signal comprises a valid frequency; generate a valid carrier indication when the incoming carrier signal is determined as having a valid frequency; and adjust the timer between at least a first timing mode of operation and a second timing mode of operation of the frequency detector in response to the determination.
    Type: Application
    Filed: March 1, 2011
    Publication date: December 12, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Philippe Freitas, Olivier Doare, Valerie Escarpit, Christophe Landez, Xavier Lhuillier