Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.

Abstract: Examples relate to an apparatus, a device, a method, and a computer program for monitoring one or more software containers being hosted by a computer system, to an apparatus, a device, a method, and a computer program for generating information on an expected behavior of software components of software containers, and to corresponding computer systems. The apparatus for monitoring the one or more software containers comprises processing circuitry configured to determine information on an expected behavior of the one or more software containers based on respective software components being executed or used within the one or more software containers. The processing circuitry is configured to determine information on a monitored behavior of the one or more software containers. The processing circuitry is configured to determine a fault condition of a software container based on a deviation between the expected behavior of the software container and the monitored behavior of the software container.

Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.

Abstract: Methods and apparatus for balancing power between discrete components, such as processing units (e.g., CPUs) and accelerators in a compute node or platform. Power consumption of the compute platform is monitored to detect for conditions under which a threshold (e.g., power supply capacity threshold) is exceeded. In response, the operating frequencies of a processing unit and/or other platform components such as accelerators, are adjusted to reduce the power consumption of the platform to return below the threshold. Power limit biasing hints (scaling weights) are provided to platform components, along with a power violation index, which are used to adjust the operating frequencies of the platform components. Optionally, a processing unit can calculate the power violation index and the scaling weights and directly control the frequencies of itself and platform components. Embodiments of multi-socket platforms are also provided.

Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.

Abstract: Methods and apparatus for optimizing fault tolerance on HPC (high-performance computing) systems including systems employing exascale architectures. The method and apparatus implement one or more management/service nodes in a management/service node layer and a plurality of sub-management nodes in a sub-management node layer. The sub-management nodes implement redundant cross-connected software components in different sub-layers to provide redundant channels. The redundant software components in a lowest sub-layer are connected to switches in racks containing multiple service nodes. The sub-management nodes are configured to employ the multiple redundant channels to collect telemetry data and other data from the service nodes such that the system continues to collect the data in the event of a failure in a software component or hardware failure.

Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.

Abstract: A computing node can execute a controller in a secure and trusted environment. The controller can cause a task to be executed on different nodes with differing computing platform software and an executable derived from a different coding language. The controller can detect anomalies in results from performance of the task using the different nodes. Any node with an anomalous result can be excluded from use and considered compromised by intrusion. The controller can also at some time interval or a pseudo-random time interval, change computing software settings and/or coding language used for applications on the node.

Abstract: According to various embodiments, a cross-feedback phase-locked loop (XF-PLL) may include a secondary phase/frequency detector to detect the phase/frequency differences between two adjacent domains and feed the phase/frequency differences back into the main feedback loop of the XF-PLL, thereby reducing accumulated jitter and inter-domain clock skew in a distributed clocking system. Other embodiments may be described and claimed.

Abstract: In some embodiments of the invention, a processor with a power management scheme using dynamically switchable embedded power gates.