Abstract: An embodiment device comprises a first processing unit configured to process an initial data line and deliver a first processed data line, a first delay unit coupled to the output of the first processing unit and configured to deliver a delayed first processed data line delayed by a first delay, a second delay unit configured to deliver the delayed initial data line delayed by a second delay, a second processing unit coupled to the output of the second delay unit and configured to process the delayed initial data line and deliver a delayed second processed data line, and a comparison unit configured to compare the contents of the delayed first and second processed data lines and deliver a non-authentication signal if the contents are not identical, the first and second delays being equal to a variable value.

Abstract: An embodiment device comprises a first processing unit configured to process an initial data line and deliver a first processed data line, a first delay unit coupled to the output of the first processing unit and configured to deliver a delayed first processed data line delayed by a first delay, a second delay unit configured to deliver the delayed initial data line delayed by a second delay, a second processing unit coupled to the output of the second delay unit and configured to process the delayed initial data line and deliver a delayed second processed data line, and a comparison unit configured to compare the contents of the delayed first and second processed data lines and deliver a non-authentication signal if the contents are not identical, the first and second delays being equal to a variable value.

Abstract: The invention relates to a method of testing an integrated circuit comprising memory cells arranged around a core whose clock input is subjected to a conditional inhibition in the test mode. The method in accordance with the invention includes the following steps: configuration of the circuit in the test mode (T/R=1, TM, En=0), selection of a virtual address (Sel(DV)), canceling the inhibition (En=1) of the clock input of the core following said selection. The invention enables to transfer to the core enough clock pulses to allow the core to properly achieve the operating sequence that it should emulate, without resorting to prior storage of the number of pulses necessary for this operating sequence. The inhibition of the clock input of the core can be controlled by means of JTAG-compliant series of instructions. Application: Validation of the functioning of integrated circuits.

Abstract: The present invention relates to a method for optimization of temporal performances of a network of electronic cells, comprising a plurality of cells which are taken from a library (LIB), comprising several categories of cells, the cells of a same category all having the same functionality, and being arranged in increasing order of power.

Abstract: An arithmetic unit configured to perform multiply and add operations on three operands A, B and C, where A is the multiplicand, B is the multiplier and C is the addend. The arithmetic unit includes a multiplier unit having an input stage configured to receive operands A and B from a data pump and includes an output to provide a product AB. The arithmetic unit also includes a register having an input coupled to the multiplier unit output and an output and a multiplexer having a first data input coupled to the multiplier unit output, a second data input coupled to the register output, a toggle command input and a data output. A bypass decision block in the arithmetic unit includes an input stage configured to receive the operands A and B and includes an output coupled to a scheduler and to the toggle command input.

Abstract: The invention relates to a method of testing an integrated circuit comprising memory cells arranged around a core whose clock input is subjected to a conditional inhibition in the test mode.