Abstract: Various embodiments include techniques for performing self-synchronizing remote memory operations in a multiprocessor computing system. During a remote memory operation in the multiprocessor computing system, a source processing unit transmits multiple segments of data to a destination processing. For each segment of data, the source processing unit transmits a remote memory operation to the destination processing unit that includes associated metadata that identifies the memory location of a corresponding synchronization object. The remote memory operation along with the metadata is transmitted as a single unit to the destination processing unit. The destination processing unit splits the operation into the remote memory operation and the memory synchronization operation. As a result, the source processing unit avoids the need to perform a separate memory synchronization operation, thereby reducing inter-processor communications and increasing performance of remote memory operations.

Abstract: Various embodiments include techniques for performing self-synchronizing remote memory operations in a data center or multiprocessor computing system. During a remote memory operation, a source processor transmits multiple data segments to a destination processor. For each data segment, the source processor transmits a remote memory operation to the destination processor that includes associated metadata that identifies the memory location of a corresponding synchronization object representing a count of data segments to be stored or a flag for each data segment to be stored. The remote memory operation along with the metadata is transmitted as a single unit to the destination processor. The destination processor splits the operation into the remote memory operation and the memory synchronization operation.

Abstract: Various embodiments include techniques for performing self-synchronizing remote memory operations in a multiprocessor computing system. During a remote memory operation in the multiprocessor computing system, a source processing unit transmits multiple segments of data to a destination processing. For each segment of data, the source processing unit transmits a remote memory operation to the destination processing unit that includes associated metadata that identifies the memory location of a corresponding synchronization object. The remote memory operation along with the metadata is transmitted as a single unit to the destination processing unit. The destination processing unit splits the operation into the remote memory operation and the memory synchronization operation. As a result, the source processing unit avoids the need to perform a separate memory synchronization operation, thereby reducing inter-processor communications and increasing performance of remote memory operations.

Abstract: Apparatuses, systems, and techniques to perform an application programming interface (API) to select a single thread from a group of threads to perform a set of instructions. In at least one embodiment, processors or computer systems are to perform an API to indicate instructions to be performed by a single thread and to select that thread from a group of threads to perform said instructions.

Abstract: Apparatuses, systems, and techniques to perform an application programming interface (API) to select a single thread from a group of threads to perform a set of instructions and to broadcast a result of performance of said set of instructions to said group of threads. In at least one embodiment, processors or computer systems are to perform an API to indicate instructions to be performed by a single thread and to select that thread from a group of threads to perform said instructions, and to make available to said group of threads data generated as a result of performance of said instructions.

Abstract: Apparatuses, systems, and techniques to check memory transaction information. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to check for information provided in a token by one or more users about one or more memory transactions after a first amount of time indicated by one or more users.

Abstract: Apparatuses, systems, and techniques to provide memory transaction information. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information about one or more memory transactions to be provided to one or more users.

Abstract: Apparatuses, systems, and techniques to perform a graphics processing unit (GPU) prefetch instruction to cause a variable amount of information to be stored into one or more GPU caches. In at least one embodiment, one or more circuits of a GPU are to perform a GPU prefetch instruction to cause a variable amount of information to be stored into one or more GPU caches.

Abstract: Apparatuses, systems, and techniques to transform information corresponding to one or more memory transactions. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information corresponding to one or more memory transactions resulting from performance of the API to be transformed.

Abstract: Apparatuses, systems, and techniques to perform a tensor prefetch instruction to cause one or more tensors to be transformed and stored into one or more caches. In at least one embodiment, one or more circuits of a GPU are to perform a tensor prefetch instruction to cause one or more tensors to be transformed and stored into one or more GPU caches.

Abstract: Apparatuses, systems, and techniques to perform delayed memory transaction information check. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to check for information provided by one or more users about one or more memory transactions after a timeout event indicated by one or more users.

Abstract: Apparatuses, systems, and techniques to transform and store information corresponding to one or more memory transactions. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information corresponding to one or more memory transactions resulting from performance of the API to be transformed and stored.

Abstract: Apparatuses, systems, and techniques to store information in a plurality of storage locations allocated to a graphics processing unit (GPU). In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information to be stored in a plurality of storage locations allocated to a first GPU.

Abstract: Apparatuses, systems, and techniques to cause information to be provided. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause an amount of information to be accessed as a result of one or more memory transactions to be provided to one or more users.

Abstract: Apparatuses, systems, and techniques to create one or more memory transaction software objects. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause one or more software objects to indicate whether one or more memory transactions have been performed.

Abstract: Apparatuses, systems, and techniques to indicate storage locations of information to be mapped from a first tensor to a second tensor. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to indicate one or more storage locations of information to be mapped from a first tensor to a second tensor.

Abstract: Apparatuses, systems, and techniques to facilitate asynchronous data movement accounting. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause one or more memory transactions to be performed without storing information about the one or more memory transactions.

Abstract: Apparatuses, systems, and techniques to cause a first tensor to be translated into a second tensor according to a tensor map. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause a first tensor to be translated into a second tensor according to a tensor map.

Abstract: Apparatuses, systems, and techniques to generate a tensor mapping. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause a mapping from a first tensor to a second tensor to be generated.

Abstract: Apparatuses, systems, and techniques to store memory transaction information. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information received by the API about one or more memory transactions to be stored.