Patents by Inventor Olivier Gourhant

Olivier Gourhant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9437498
    Abstract: A method is for forming at least two different gates metal regions of at least two MOS transistors. The method may include forming a metal layer on a gate dielectric layer; and forming a metal hard mask on the metal layer, with the hard mask having a composition different from that of the metal layer and covering a first region of the metal layer and leaving open a second region of the metal layer. The method may also include diffusion annealing the intermediate structure obtained in the prior steps such as to make the metal atoms of the hard mask diffuse into the first region, and removal of the hard mask.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: September 6, 2016
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Stéphane Zoll, Philippe Garnier, Olivier Gourhant, Vincent Joseph
  • Publication number: 20150262884
    Abstract: A method is for forming at least two different gates metal regions of at least two MOS transistors. The method may include forming a metal layer on a gate dielectric layer; and forming a metal hard mask on the metal layer, with the hard mask having a composition different from that of the metal layer and covering a first region of the metal layer and leaving open a second region of the metal layer. The method may also include diffusion annealing the intermediate structure obtained in the prior steps such as to make the metal atoms of the hard mask diffuse into the first region, and removal of the hard mask.
    Type: Application
    Filed: March 3, 2015
    Publication date: September 17, 2015
    Inventors: Stéphane ZOLL, Philippe GARNIER, Olivier GOURHANT, Vincent JOSEPH
  • Patent number: 8802575
    Abstract: A method for forming the gate insulator of a MOS transistor, including the steps of: a) forming a thin silicon oxide layer at the surface of a semiconductor substrate; b) incorporating nitrogen atoms into the silicon oxide layer by plasma nitridation at a temperature lower than 200° C., to transform this layer into a silicon oxynitride layer; and c) coating the silicon oxynitride layer with a layer of a material of high dielectric constant, wherein steps b) and c) follow each other with no intermediate anneal step.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: August 12, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Olivier Gourhant, David Barge, Clément Gaumer, Mickaël Gros-Jean
  • Patent number: 8603887
    Abstract: A method for depositing a silicon oxide layer on a substrate including a silicon region and a silicon-germanium region, including the steps of: forming a very thin silicon layer having a thickness ranging from 0.1 to 1 nm above silicon-germanium; and depositing a silicon oxide layer on the substrate.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: December 10, 2013
    Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS, International Business Machines Corporation
    Inventors: Didier Dutartre, Nicolas Breil, Yves Campidelli, Olivier Gourhant
  • Publication number: 20130072032
    Abstract: A method for depositing a silicon oxide layer on a substrate including a silicon region and a silicon-germanium region, including the steps of: forming a very thin silicon layer having a thickness ranging from 0.1 to 1 nm above silicon-germanium; and depositing a silicon oxide layer on the substrate.
    Type: Application
    Filed: July 27, 2012
    Publication date: March 21, 2013
    Applicants: STMicroelectronics S.A., International Business Machines Corporation, STMicroelectronics (Crolles 2) SAS
    Inventors: Didier Dutartre, Nicolas Breil, Yves Campidelli, Olivier Gourhant
  • Publication number: 20120270410
    Abstract: A method for forming the gate insulator of a MOS transistor, including the steps of: a) forming a thin silicon oxide layer at the surface of a semiconductor substrate; b) incorporating nitrogen atoms into the silicon oxide layer by plasma nitridation at a temperature lower than 200° C., to transform this layer into a silicon oxynitride layer; and c) coating the silicon oxynitride layer with a layer of a material of high dielectric constant, wherein steps b) and c) follow each other with no intermediate anneal step.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 25, 2012
    Inventors: Olivier Gourhant, David Barge, Clément Gaumer, Mickaël Gros-Jean