Patents by Inventor Olivier Guiller

Olivier Guiller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for producing a capacitor
    Patent number: 9728337
    Abstract: A method for producing a capacitor stack in one portion of a substrate, the method including: forming a cavity along a thickness of the portion of the substrate from an upper face of the substrate, depositing a plurality of layers contributing to the capacitor stack onto the wall of the cavity and onto the surface of the upper face, and removing matter from the layers until the surface of the upper face is reached. The forming of the cavity includes forming at least one trench and, associated with each trench, at least one box. The at least one trench includes a trench outlet that opens into the box. The box includes a box outlet that opens at the surface of the upper face, and the box outlet being shaped to be larger than the trench outlet.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: August 8, 2017
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS SA
    Inventors: Yann Lamy, Olivier Guiller, Sylvain Joblot
  • Process for producing a through-silicon via and a through-silicon capacitor in a substrate, and corresponding device
    Patent number: 9224796
    Abstract: A device includes a substrate and an integrated-circuit interconnect on a first side. A capacitor passes through the substrate possessing a first electrode having a first contact face electrically coupled to a first electrically conductive zone placed on a second side of the substrate and a second electrode electrically coupled to the interconnect. A through-silicon via passes through the substrate having at one end a first contact face electrically coupled to a second electrically conductive zone placed on said second side of the substrate and at the other end a part electrically coupled to the interconnect part. The two first contact faces are located in the same plane.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: December 29, 2015
    Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Jean-Philippe Colonna, Sylvain Joblot, Thierry Mourier, Olivier Guiller
  • METHOD FOR PRODUCING A CAPACITOR
    Publication number: 20150206662
    Abstract: A method for producing a capacitor stack in one portion of a substrate, the method including: forming a cavity along a thickness of the portion of the substrate from an upper face of the substrate, depositing a plurality of layers contributing to the capacitor stack onto the wall of the cavity and onto the surface of the upper face, and removing matter from the layers until the surface of the upper face is reached. The forming of the cavity includes forming at least one trench and, associated with each trench, at least one box. The at least one trench includes a trench outlet that opens into the box. The box includes a box outlet that opens at the surface of the upper face, and the box outlet being shaped to be larger than the trench outlet.
    Type: Application
    Filed: July 12, 2013
    Publication date: July 23, 2015
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT, STMICROELECTRONICS SA
    Inventors: Yann Lamy, Olivier Guiller, Sylvain Joblot
  • PROCESS FOR PRODUCING A THROUGH-SILICON VIA AND A THROUGH-SILICON CAPACITOR IN A SUBSTRATE, AND CORRESPONDING DEVICE
    Publication number: 20140367828
    Abstract: A device includes a substrate and an integrated-circuit interconnect on a first side. A capacitor passes through the substrate possessing a first electrode having a first contact face electrically coupled to a first electrically conductive zone placed on a second side of the substrate and a second electrode electrically coupled to the interconnect. A through-silicon via passes through the substrate having at one end a first contact face electrically coupled to a second electrically conductive zone placed on said second side of the substrate and at the other end a part electrically coupled to the interconnect part. The two first contact faces are located in the same plane.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 18, 2014
    Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat a L'Energie Atomique et aux Energies Alternatives
    Inventors: Jean-Philippe Colonna, Sylvain Joblot, Thierry Mourier, Olivier Guiller