Abstract: A system for testing an application-specific integrated circuit, includes a characterization integrated circuit comprising at least two configurable test structures and a test assembly comprising: a device for controlling the characterization integrated circuit, configured to vary at least one physical parameter of at least one configurable test structure, an interface for receiving at least one description of an application-specific integrated circuit and extracting at least one path, a configuration device for activating and interconnecting at least one subset of the logic cells of at least one degraded test structure and of at least one non-degraded test structure, so that they each produce a topology identical to a portion of an extracted path, a measurement control device for performing at least one first measurement of a physical variable on the degraded test structure and at least one second measurement, identical to the first measurement, on the non-degraded test structure.

Abstract: A system for testing an application-specific integrated circuit, includes a characterization integrated circuit comprising at least two configurable test structures and a test assembly comprising: a device for controlling the characterization integrated circuit, configured to vary at least one physical parameter of at least one configurable test structure, an interface for receiving at least one description of an application-specific integrated circuit and extracting at least one path, a configuration device for activating and interconnecting at least one subset of the logic cells of at least one degraded test structure and of at least one non-degraded test structure, so that they each produce a topology identical to a portion of an extracted path, a measurement control device for performing at least one first measurement of a physical variable on the degraded test structure and at least one second measurement, identical to the first measurement, on the non-degraded test structure.

Abstract: A method implemented by computer, for selecting representative paths for the analysis of the behavior of an integrated circuit according to a predefined analysis strategy, comprises the identification of the set of paths of the integrated circuit having logic gates and the construction of a list of the set of the paths. The method comprises: the selection of several criteria related to the behavior of the integrated circuit, chosen from among the following types: topology, usage, sensitivity, environment, criticality; the determination of values of the selected criteria for each of the identified paths; the application of a correlation function to aggregate the set of the values of criteria to define an aggregation criterion value; and the selection of a subset of representative paths from among the list of the paths, as a function of the value of the aggregation criterion of the paths and of the predefined analysis strategy.

Abstract: The invention concerns a method of determining the effect of aging on a propagation delay in a circuit path of a digital circuit, the method comprising determining, by a processing device (104) of the digital circuit based on a parameter aging model (?pvth) representing a variation of a first parameter (p) as a function of at least the age of the digital circuit, a variation of the first parameter due to aging at a time t after fabrication of the digital circuit, wherein the first parameter (p) is a parameter of a delay model (DELAY MODEL) representing the propagation delay in the circuit path.

Abstract: A method for analyzing the behavior of an integrated circuit implemented by computer comprises: the extraction of the names of the physical components described at the RTL (or higher) level, therefore of the physical components represented, as well as the names of the modules; the extraction of the names of the physical components of a path of the circuit at the logic gate level; the labeling of the names of the physical components of the paths with the names of the known physical components or the names of the parent modules; the extraction of the physical parameters of results of simulation/analysis of the circuit at the higher level. The output is composed of associative arrays containing the physical parameters of the physical components described at the envisaged level; the assignment of the physical parameters determined in the previous step, to the labeled components of the paths.

Abstract: A method for analyzing the behavior of an integrated circuit implemented by computer comprises: the extraction of the names of the physical components described at the RTL (or higher) level, therefore of the physical components represented, as well as the names of the modules; the extraction of the names of the physical components of a path of the circuit at the logic gate level; the labeling of the names of the physical components of the paths with the names of the known physical components or the names of the parent modules; the extraction of the physical parameters of results of simulation/analysis of the circuit at the higher level. The output is composed of associative arrays containing the physical parameters of the physical components described at the envisaged level; the assignment of the physical parameters determined in the previous step, to the labeled components of the paths.

Abstract: A method implemented by computer, for selecting representative paths for the analysis of the behavior of an integrated circuit according to a predefined analysis strategy, comprises the identification of the set of paths of the integrated circuit having logic gates and the construction of a list of the set of the paths. The method comprises: the selection of several criteria related to the behavior of the integrated circuit, chosen from among the following types: topology, usage, sensitivity, environment, criticality; the determination of values of the selected criteria for each of the identified paths; the application of a correlation function to aggregate the set of the values of criteria to define an aggregation criterion value; and the selection of a subset of representative paths from among the list of the paths, as a function of the value of the aggregation criterion of the paths and of the predefined analysis strategy.

Abstract: A method for selecting, from a plurality of processing resources capable in an information-processing system of carrying out one and the same type of process, one of the resources so that it carries out a process of said type, the method including estimating the probable time to failure for each of the resources, the resource being selected so that the probable times to failure of the resources evolve in a substantially identical manner.

Abstract: The present invention relates to a parametric scan register and a method of testing a digital circuit with the aid of such a register. The parametric scan register includes a memory cell having at least one data input, able to receive a test datum, and transferring to its output a representative signal indicative of the test datum by use of a synchronization signal. It furthermore includes a parametric test block one input of which is linked to the output (s) of the cell, the output signal of the cell being transferred at the output of the parametric test block through an internal module, this internal module operating according to modes able to modify the output signal of the cell. Embodiments of the invention apply to the testing of integrated circuits with high integration density, for example in the field of nanotechnologies.