Abstract: A device for controlling the efficiency of a scanning active antenna includes at least two transmission paths Txi, a transmission path comprising a phase control module, and a power stage at the output of which a radiating element is arranged, comprising at least: a voltage modulator located upstream of the power stage of each of the radiating elements, a control device transmitting a PWM drain voltage control signal configured so as to manage the gain of a power stage in accordance with a predefined first bias law and to control the phase applied to the drain of the power stage in accordance with a second bias law.

Abstract: A system for adapting the voltage of a drain of a power stage includes at least two transmission paths TXa, a transmission path comprising a resistive element (1n), a phase control module (2n), and a power stage (3n) at the output of which a radiating element (En) is arranged, comprising at least: a device (5n) for determining the value of a reflected power Pr, the value of an incident power Pi in a power stage, and the ratio of the powers R, an analogue device (6n) configured so as to pulse width-modulate the difference signal, a switching cell (7n) receiving a low-power PWM signal and designed to generate a power signal PWMa that is transformed, by a low-pass filter (8n), into a bias signal for biasing the power stage in accordance with a predefined bias control law.

Abstract: A device for controlling the efficiency of a scanning active antenna includes at least two transmission paths Txi, a transmission path comprising a phase control module, and a power stage at the output of which a radiating element is arranged, comprising at least: a voltage modulator located upstream of the power stage of each of the radiating elements, a control device transmitting a PWM drain voltage control signal configured so as to manage the gain of a power stage in accordance with a predefined first bias law and to control the phase applied to the drain of the power stage in accordance with a second bias law.

Abstract: A system for adapting the voltage of a drain of a power stage includes at least two transmission paths TXa, a transmission path comprising a resistive element (1n), a phase control module (2n), and a power stage (3n) at the output of which a radiating element (En) is arranged, comprising at least: a device (5n) for determining the value of a reflected power Pr, the value of an incident power Pi in a power stage, and the ratio of the powers R, an analogue device (6n) configured so as to pulse width-modulate the difference signal, a switching cell (7n) receiving a low-power PWM signal and designed to generate a power signal PWMa that is transformed, by a low-pass filter (8n), into a bias signal for biasing the power stage in accordance with a predefined bias control law.

Abstract: A power switching cell, and associated multi-level converter, include an input port capable of receiving a switching control signal, an input transistor linked by the gate to the input port, and by the source to a reference voltage, a self-biasing circuit comprising a self-biasing transistor linked by the gate to the drain of the input transistor, and a resistor connected in parallel between the gate and the source of the self-biasing transistor, and in series between the drain of the input transistor and the source of the self-biasing transistor, a power transistor, linked by the gate to the source of the self-biasing transistor and by the drain to a power supply voltage, and an isolating transistor linked by the gate and by the source to the gate and to the source of the power transistor, and by the drain to the output port of the cell.

Abstract: A power switching cell, and associated multi-level converter, include an input port capable of receiving a switching control signal, an input transistor linked by the gate to the input port, and by the source to a reference voltage, a self-biasing circuit comprising a self-biasing transistor linked by the gate to the drain of the input transistor, and a resistor connected in parallel between the gate and the source of the self-biasing transistor, and in series between the drain of the input transistor and the source of the self-biasing transistor, a power transistor, linked by the gate to the source of the self-biasing transistor and by the drain to a power supply voltage, and an isolating transistor linked by the gate and by the source to the gate and to the source of the power transistor, and by the drain to the output port of the cell.

Abstract: A power switching cell with normally on field-effect transistors comprises a current switch receiving the control input signal over an activation input and a power transistor for switching a high voltage VDD applied to its drain, to its source that is connected to the output port of the cell. The control of the gate of the power transistor whose source is floating, according to the input signal, is provided by a self-biasing circuit connected between its gate and source. The current switch is connected between the self-biasing circuit and a zero or negative reference voltage. The self-biasing circuit comprises a transistor whose source or drain is connected to the gate or source of the power transistor. The gate of this transistor is biased by a resistor connected between its gate and source, and between the current switch and the source. The transistors are HEMT transistors using GaN or AsGa technology.

Abstract: A stack along a z-axis for a high-electron-mobility field-effect transistor, comprises: a buffer layer comprising a first semiconductor material comprising a binary, ternary or quaternary nitride compound having a first bandgap, a barrier layer comprising a second semiconductor material comprising a binary, ternary or quaternary nitride compound and having a second bandgap, the second bandgap wider than the first bandgap, a heterojunction between the buffer and barrier layers and, a two-dimensional electron gas located in an XY plane perpendicular to the z-axis and in the vicinity of the heterojunction wherein: the buffer layer comprises a zone comprising fixed negative charges of density per unit volume higher than or equal to 1017 cm?3, the zone having a thickness smaller than or equal to 200 nm, the product of multiplication of the density per unit volume of fixed negative charges by the thickness of the zone between 1012 cm?2 and 3.1013 cm?2.

Abstract: A stack along a z-axis for a high-electron-mobility field-effect transistor, comprises: a buffer layer comprising a first semiconductor material comprising a binary, ternary or quaternary nitride compound having a first bandgap, a barrier layer comprising a second semiconductor material comprising a binary, ternary or quaternary nitride compound and having a second bandgap, the second bandgap wider than the first bandgap, a heterojunction between the buffer and barrier layers and, a two-dimensional electron gas located in an XY plane perpendicular to the z-axis and in the vicinity of the heterojunction wherein: the buffer layer comprises a zone comprising fixed negative charges of density per unit volume higher than or equal to 1017 cm?3, the zone having a thickness smaller than or equal to 200 nm, the product of multiplication of the density per unit volume of fixed negative charges by the thickness of the zone between 1012 cm?2 and 3.1013 cm?2.

Abstract: A power switching cell with normally on field-effect transistors comprises a current switch receiving the control input signal over an activation input and a power transistor for switching a high voltage VDD applied to its drain, to its source that is connected to the output port of the cell. The control of the gate of the power transistor whose source is floating, according to the input signal, is provided by a self-biasing circuit connected between its gate and source. The current switch is connected between the self-biasing circuit and a zero or negative reference voltage. The self-biasing circuit comprises a transistor whose source or drain is connected to the gate or source of the power transistor. The gate of this transistor is biased by a resistor connected between its gate and source, and between the current switch and the source. The transistors are HEMT transistors using GaN or AsGa technology.