Patents by Inventor Olivier Laurent Peyran

Olivier Laurent Peyran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090071972
    Abstract: A method and apparatus for providing an exchange of multimedia products between a plurality of users is disclosed. For example, a user has a multimedia product to be given up in exchange for either another product desired or exchangeable denomination of value, including cash and/or value points, which may be used in exchange to acquire said multimedia product desired. The method includes collating each user's exchange criteria into a data system, matching a user willing to part with a multimedia product with another user desiring said multimedia product in said data system; collecting said multimedia product desired from said willing user; and dispensing said multimedia product desired to said desiring user. A mutual exchange between 2 matched users is also possible. Kiosks housing a jukebox-like apparatus for depositing and retrieving the products which are in operative control by a data system implemented over the Internet are also disclosed.
    Type: Application
    Filed: May 10, 2007
    Publication date: March 19, 2009
    Inventors: Olivier Laurent Peyran, May Chin Tan, Gamaliel Amaudruz
  • Publication number: 20030188271
    Abstract: The invention relates to an IC chip-planning system and method to provide automatic creation and optimisation of chip-level design plan alternatives that can meet user-specific target chip area/design density, chip shape/aspect ratio, delay/timing closure, and/or congestion/routability objectives at each level of the design—architectural, RTL, gate, structural and physical levels. By combining global searching and local searching, a multi-objective optimisation process and a single-objective optimisation process, the invention can greatly reduce searching and optimisation time. Flexible system structure allows for generation of the optimised chip-planning solutions via an open optimisation train, a small optimisation loop, and/or a large optimisation loop.
    Type: Application
    Filed: September 30, 2002
    Publication date: October 2, 2003
    Applicant: Institute of High Performance Computing
    Inventors: Wenjun Zhuang, Olivier Laurent Peyran, Zheng Zeng, Ping Bai