Abstract: The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state.

Abstract: The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state.

Abstract: The invention relates to a production process for a flash memory from a semi-conductor substrate fitted with at least two adjacent rows of precursor stacks of floating gate transistors, the precursor stacks being at least partially covered by a protective resin and being separated by a formation zone for a source line. The process includes forming a trench in the formation zone for the source line by an attack of this zone and of the protective resin. The result of the attack step includes a deposit of residue from the resin below the precursor stacks. The residue deposit is removed. A source line is implanted in the formation zone below the precursor stacks. This process enables the time needed for erasing the memory to be reduced.

Abstract: The invention relates to a production process for a flash memory from a semi-conductor substrate fitted with at least two adjacent rows of precursor stacks of floating gate transistors, the precursor stacks being at least partially covered by a protective resin and being separated by a formation zone for a source line. The process includes forming a trench in the formation zone for the source line by an attack of this zone and of the protective resin. The result of the attack step includes a deposit of residue from the resin below the precursor stacks. The residue deposit is removed. A source line is implanted in the formation zone below the precursor stacks. This process enables the time needed for erasing the memory to be reduced.

Abstract: An oscillator circuit produces first and second oscillating logic signals that are of a same frequency and are non-overlapping in a first logic state. This oscillator includes a flip-flop circuit to produce third and fourth oscillating logic signals of opposite polarities, this flip-flop circuit being driven by first and second driving logic signals. First and second logic gates receive the third and fourth logic signals and produce the first and second logic signals, the logic state transitions in the first and second logic signals being produced as a function of the logic state transitions of the third and fourth logic signals. The first and second logic gates are organized so as to introduce a delay into the transitions from a second logic state to the first logic state, in the first and second logic signals, with respect to transitions in the third and fourth logic signals.

Abstract: A structure of electronic devices integrated in a semiconductor substrate with a first type of conductivity comprising at least a first HV transistor and at least a second LV transistor, each having a corresponding gate region. Said first HV transistor has lightly doped drain and source regions with a second type of conductivity, and said second LV transistor has respective drain and source regions with the second type of conductivity, each including a lightly doped portion adjacent to the respective gate region and a second portion which is more heavily doped and comprises a silicide layer.

Abstract: A structure of electronic devices integrated in a semiconductor substrate with a first type of conductivity comprising at least a first HV transistor and at least a second LV transistor, each having a corresponding gate region. Said first HV transistor has lightly doped drain and source regions with a second type of conductivity, and said second LV transistor has respective drain and source regions with the second type of conductivity, each including a lightly doped portion adjacent to the respective gate region and a second portion which is more heavily doped and comprises a silicide layer.

Abstract: An oscillator circuit produces first and second oscillating logic signals that are of a same frequency and are non-overlapping in a first logic state. This oscillator includes a flip-flop circuit to produce third and fourth oscillating logic signals of opposite polarities, this flip-flop circuit being driven by first and second driving logic signals. First and second logic gates receive the third and fourth logic signals and produce the first and second logic signals, the logic state transitions in the first and second logic signals being produced as a function of the logic state transitions of the third and fourth logic signals. The first and second logic gates are organized so as to introduce a delay into the transitions from a second logic state to the first logic state, in the first and second logic signals, with respect to transitions in the third and fourth logic signals.