Patents by Inventor Olivier Temam
Olivier Temam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966833Abstract: A computing unit for accelerating a neural network is disclosed. The computing unit may include an input unit that includes a digital-to-analog conversion unit and an analog-to-digital conversion unit that is configured to receive an analog signal from the output of a last interconnected analog crossbar circuit of a plurality of analog crossbar circuits and convert the second analog signal into a digital output vector, and a plurality of interconnected analog crossbar circuits that include the first interconnected analog crossbar circuit and the last interconnected crossbar circuits, wherein a second interconnected analog crossbar circuit of the plurality of interconnected analog crossbar circuits is configured to receive a third analog signal from another interconnected analog crossbar circuit of the plurality of interconnected crossbar circuits and perform one or more operations on the third analog signal based on the matrix weights stored by the crosspoints of the second interconnected analog crossbar.Type: GrantFiled: August 9, 2018Date of Patent: April 23, 2024Assignee: Google LLCInventors: Pierre-Luc Cantin, Olivier Temam
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Patent number: 11948060Abstract: A three dimensional neural network accelerator that includes a first neural network accelerator tile that includes a first transmission coil, and a second neural network accelerator tile that includes a second transmission coil, wherein the first neural network accelerator tile is adjacent to and aligned vertically with the second neural network accelerator tile, and wherein the first transmission coil is configured to wirelessly communicate with the second transmission coil via inductive coupling.Type: GrantFiled: January 7, 2022Date of Patent: April 2, 2024Assignee: GOOGLE LLCInventors: Andreas Georg Nowatzyk, Olivier Temam, Ravi Narayanaswami, Uday Kumar Dasari
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Patent number: 11940946Abstract: A vector reduction circuit configured to reduce an input vector of elements comprises a plurality of cells, wherein each of the plurality of cells other than a designated first cell that receives a designated first element of the input vector is configured to receive a particular element of the input vector, receive, from another of the one or more cells, a temporary reduction element, perform a reduction operation using the particular element and the temporary reduction element, and provide, as a new temporary reduction element, a result of performing the reduction operation using the particular element and the temporary reduction element. The vector reduction circuit also comprises an output circuit configured to provide, for output as a reduction of the input vector, a new temporary reduction element corresponding to a result of performing the reduction operation using a last element of the input vector.Type: GrantFiled: June 22, 2021Date of Patent: March 26, 2024Assignee: Google LLCInventors: Gregory Michael Thorson, Andrew Everett Phelps, Olivier Temam
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Publication number: 20240078417Abstract: One embodiment of an accelerator includes a computing unit; a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations, the second memory bank configured to store a sufficient amount of the neural network parameters on the computing unit to allow for latency below a specified level with throughput above a specified level. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs computations associated with at least one element of a data array, the one or more computations performed by the MAC operator.Type: ApplicationFiled: June 30, 2023Publication date: March 7, 2024Inventors: Olivier Temam, Harshit Khaitan, Ravi Narayanaswami, Dong Hyuk Woo
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Patent number: 11836598Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.Type: GrantFiled: March 26, 2021Date of Patent: December 5, 2023Assignee: Google LLCInventors: Andreas Georg Nowatzyk, Olivier Temam
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Patent number: 11816480Abstract: A computing unit is disclosed, comprising a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs one or more computations associated with at least one element of a data array, the one or more computations being performed by the MAC operator and comprising, in part, a multiply operation of the input activation received from the data bus and a parameter received from the second memory bank.Type: GrantFiled: August 22, 2022Date of Patent: November 14, 2023Assignee: Google LLCInventors: Olivier Temam, Ravi Narayanaswami, Harshit Khaitan, Dong Hyuk Woo
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Patent number: 11748443Abstract: A circuit comprises an input register configured to receive an input vector of elements, a control register configured to receive a control vector of elements, wherein each element of the control vector corresponds to a respective element of the input vector, and wherein each element specifies a permutation of a corresponding element of the input vector, and a permute execution circuit configured to generate an output vector of elements corresponding to a permutation of the input vector. Generating each element of the output vector comprises accessing, at the input register, a particular element of the input vector, accessing, at the control register, a particular element of the control vector corresponding to the particular element of the input vector, and outputting the particular element of the input vector as an element at a particular position of the output vector that is selected based on the particular element of the control vector.Type: GrantFiled: March 22, 2021Date of Patent: September 5, 2023Assignee: Google LLCInventors: Dong Hyuk Woo, Gregory Michael Thorson, Andrew Everett Phelps, Olivier Temam, Jonathan Ross, Christopher Aaron Clark
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Patent number: 11727259Abstract: One embodiment of an accelerator includes a computing unit; a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations, the second memory bank configured to store a sufficient amount of the neural network parameters on the computing unit to allow for latency below a specified level with throughput above a specified level. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs computations associated with at least one element of a data array, the one or more computations performed by the MAC operator.Type: GrantFiled: November 10, 2022Date of Patent: August 15, 2023Assignee: Google LLCInventors: Olivier Temam, Harshit Khaitan, Ravi Narayanaswami, Dong Hyuk Woo
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Publication number: 20230004386Abstract: A computing unit is disclosed, comprising a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs one or more computations associated with at least one element of a data array, the one or more computations being performed by the MAC operator and comprising, in part, a multiply operation of the input activation received from the data bus and a parameter received from the second memory bank.Type: ApplicationFiled: August 22, 2022Publication date: January 5, 2023Inventors: Olivier Temam, Ravi Narayanaswami, Harshit Khaitan, Dong Hyuk Woo
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Patent number: 11501144Abstract: One embodiment of an accelerator includes a computing unit; a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations, the second memory bank configured to store a sufficient amount of the neural network parameters on the computing unit to allow for latency below a specified level with throughput above a specified level. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs computations associated with at least one element of a data array, the one or more computations performed by the MAC operator.Type: GrantFiled: September 12, 2019Date of Patent: November 15, 2022Assignee: Google LLCInventors: Olivier Temam, Harshit Khaitan, Ravi Narayanaswami, Dong Hyuk Woo
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Publication number: 20220358355Abstract: A circuit for performing neural network computations for a neural network is described. The circuit includes plurality of neural network layers each including a crossbar arrays. The plurality of crossbar arrays are formed in a common substrate in a stacked configuration. Each crossbar array includes a set of crosspoint devices. A respective electrical property of each of the crosspoint devices is adjustable to represent a weight value that is stored for each respective crosspoint device. A processing unit is configured to adjust the respective electrical properties of each of the crosspoint devices by pre-loading each of the crosspoint devices with a tuning signal. A value of the turning signal for each crosspoint device is a function of the weight value represented by each respective crosspoint device.Type: ApplicationFiled: May 23, 2022Publication date: November 10, 2022Inventors: Pierre-Luc Cantin, Olivier Temam
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Publication number: 20220318594Abstract: A computer-implemented method that includes receiving, by a processing unit, an instruction that specifies data values for performing a tensor computation. In response to receiving the instruction, the method may include, performing, by the processing unit, the tensor computation by executing a loop nest comprising a plurality of loops, wherein a structure of the loop nest is defined based on one or more of the data values of the instruction. The tensor computation can be at least a portion of a computation of a neural network layer. The data values specified by the instruction may comprise a value that specifies a type of the neural network layer, and the structure of the loop nest can be defined at least in part by the type of the neural network layer.Type: ApplicationFiled: June 21, 2022Publication date: October 6, 2022Inventors: Ravi Narayanaswami, Dong Hyuk Woo, Olivier Temam, Harshit Khaitan
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Patent number: 11422801Abstract: A computing unit is disclosed, comprising a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs one or more computations associated with at least one element of a data array, the one or more computations being performed by the MAC operator and comprising, in part, a multiply operation of the input activation received from the data bus and a parameter received from the second memory bank.Type: GrantFiled: January 4, 2019Date of Patent: August 23, 2022Assignee: Google LLCInventors: Olivier Temam, Ravi Narayanaswami, Harshit Khaitan, Dong Hyuk Woo
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Publication number: 20220261622Abstract: Methods, systems, and apparatus including a special purpose hardware chip for training neural networks are described. The special-purpose hardware chip may include a scalar processor configured to control computational operation of the special-purpose hardware chip. The chip may also include a vector processor configured to have a 2-dimensional array of vector processing units which all execute the same instruction in a single instruction, multiple-data manner and communicate with each other through load and store instructions of the vector processor. The chip may additionally include a matrix multiply unit that is coupled to the vector processor configured to multiply at least one two-dimensional matrix with a second one-dimensional vector or two-dimensional matrix in order to obtain a multiplication result.Type: ApplicationFiled: March 14, 2022Publication date: August 18, 2022Inventors: Thomas Norrie, Olivier Temam, Andrew Everett Phelps, Norman Paul Jouppi
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Patent number: 11379707Abstract: A computer-implemented method that includes receiving, by a processing unit, an instruction that specifies data values for performing a tensor computation. In response to receiving the instruction, the method may include, performing, by the processing unit, the tensor computation by executing a loop nest comprising a plurality of loops, wherein a structure of the loop nest is defined based on one or more of the data values of the instruction. The tensor computation can be at least a portion of a computation of a neural network layer. The data values specified by the instruction may comprise a value that specifies a type of the neural network layer, and the structure of the loop nest can be defined at least in part by the type of the neural network layer.Type: GrantFiled: November 22, 2017Date of Patent: July 5, 2022Assignee: Google LLCInventors: Ravi Narayanaswami, Dong Hyuk Woo, Olivier Temam, Harshit Khaitan
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Patent number: 11341402Abstract: A circuit for performing neural network computations for a neural network is described. The circuit includes plurality of neural network layers each including a crossbar arrays. The plurality of crossbar arrays are formed in a common substrate in a stacked configuration. Each crossbar array includes a set of crosspoint devices. A respective electrical property of each of the crosspoint devices is adjustable to represent a weight value that is stored for each respective crosspoint device. A processing unit is configured to adjust the respective electrical properties of each of the crosspoint devices by pre-loading each of the crosspoint devices with a tuning signal. A value of the turning signal for each crosspoint device is a function of the weight value represented by each respective crosspoint device.Type: GrantFiled: October 23, 2018Date of Patent: May 24, 2022Assignee: Google LLCInventors: Pierre-Luc Cantin, Olivier Temam
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Publication number: 20220147793Abstract: A three dimensional neural network accelerator that includes a first neural network accelerator tile that includes a first transmission coil, and a second neural network accelerator tile that includes a second transmission coil, wherein the first neural network accelerator tile is adjacent to and aligned vertically with the second neural network accelerator tile, and wherein the first transmission coil is configured to wirelessly communicate with the second transmission coil via inductive coupling.Type: ApplicationFiled: January 7, 2022Publication date: May 12, 2022Inventors: Andreas Georg Nowatzyk, Olivier Temam, Ravi Narayanaswami, Uday Kumar Dasari
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Patent number: 11275992Abstract: Methods, systems, and apparatus including a special purpose hardware chip for training neural networks are described. The special-purpose hardware chip may include a scalar processor configured to control computational operation of the special-purpose hardware chip. The chip may also include a vector processor configured to have a 2-dimensional array of vector processing units which all execute the same instruction in a single instruction, multiple-data manner and communicate with each other through load and store instructions of the vector processor. The chip may additionally include a matrix multiply unit that is coupled to the vector processor configured to multiply at least one two-dimensional matrix with a second one-dimensional vector or two-dimensional matrix in order to obtain a multiplication result.Type: GrantFiled: May 17, 2018Date of Patent: March 15, 2022Assignee: Google LLCInventors: Thomas Norrie, Olivier Temam, Andrew Everett Phelps, Norman Paul Jouppi
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Publication number: 20210318983Abstract: A vector reduction circuit configured to reduce an input vector of elements comprises a plurality of cells, wherein each of the plurality of cells other than a designated first cell that receives a designated first element of the input vector is configured to receive a particular element of the input vector, receive, from another of the one or more cells, a temporary reduction element, perform a reduction operation using the particular element and the temporary reduction element, and provide, as a new temporary reduction element, a result of performing the reduction operation using the particular element and the temporary reduction element. The vector reduction circuit also comprises an output circuit configured to provide, for output as a reduction of the input vector, a new temporary reduction element corresponding to a result of performing the reduction operation using a last element of the input vector.Type: ApplicationFiled: June 22, 2021Publication date: October 14, 2021Inventors: Gregory Michael Thorson, Andrew Everett Phelps, Olivier Temam
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Publication number: 20210312011Abstract: A circuit comprises an input register configured to receive an input vector of elements, a control register configured to receive a control vector of elements, wherein each element of the control vector corresponds to a respective element of the input vector, and wherein each element specifies a permutation of a corresponding element of the input vector, and a permute execution circuit configured to generate an output vector of elements corresponding to a permutation of the input vector. Generating each element of the output vector comprises accessing, at the input register, a particular element of the input vector, accessing, at the control register, a particular element of the control vector corresponding to the particular element of the input vector, and outputting the particular element of the input vector as an element at a particular position of the output vector that is selected based on the particular element of the control vector.Type: ApplicationFiled: March 22, 2021Publication date: October 7, 2021Inventors: Dong Hyuk Woo, Gregory Michael Thorson, Andrew Everett Phelps, Olivier Temam, Jonathan Ross, Christopher Aaron Clark