Abstract: A latch assembly for a closure panel and corresponding method of operation are provided. The assembly includes an actuation group to latch and unlatch the closure panel using power from a main power source during normal operation. A first backup energy source is selectively coupled to the actuation group and stores energy during normal operation and supplies the energy during a failure. A second backup energy source is selectively coupled to the first backup energy source and supplies energy thereto during the failure. A latch controller is coupled to the backup energy sources and detects latch operation and whether there is normal operation. The latch controller charges the first backup energy source using energy from the second backup energy source based on the detection of latch operation and the failure and disconnects the second backup energy source during normal operation to conserve energy stored in the second backup energy source.

Abstract: A method, power converter and controller are disclosed for controlling a power converter having a main converter connected between a first input voltage and a ground and having a main output at an output terminal, an auxiliary converter connected between a second input voltage and the ground and having an auxiliary output, an output capacitor connected between the main output terminal and a ground, and an auxiliary capacitor connected between the auxiliary output and the main output terminal; and a controller; the method comprising: operating the main converter at a first frequency, operating the auxiliary converter at a second frequency; controlling the main converter to control the voltage at the auxiliary output; and controlling the auxiliary converter to control the voltage at the main output.

Abstract: Disclosed are a controller and power converter having a main buck converter connected between a first input voltage and ground and having a main output, a bidirectional auxiliary converter connected between a second terminal and ground and having an auxiliary output connected to the main output, an output capacitor, and an auxiliary capacitor connected between the second terminal and the ground for providing a second terminal voltage at the second terminal; the controller comprising: first control circuit configured to operate the main converter at a first frequency; and second control circuit configured to operate the auxiliary converter at a higher frequency; the first control circuit being further configured to operate the main converter in dependence on the second terminal voltage; and the second control circuit being further configured to operate the auxiliary converter to control the voltage at the main output terminal.

Abstract: A power-hub for an electric vehicle and operating modes thereof are disclosed herein. The disclosed power-hub is designed to operate in the Vehicle-to Grid (V2G), Grid-to-Vehicle (G2V), Vehicle-to-Home (V2H), and Vehicle-to-Vehicle (V2V) operating modes. When operating in the V2V mode, the power-hub is configured to allow for sending DC power through a conventional AC power port, with all the associated ratings and constraints from the AC design, in order to achieve higher power transfer and efficiency for V2V operation. A digital Hysteretic Current Mode Control (HCMC) scheme is disclosed and the efficiency and loss distribution of four operating modes are disclosed for the power-hub: 1) DC-AC Boundary Conduction Mode (BCM), 2) DC-AC Continuous Conduction Mode (CCM)/BCM hybrid, 3) DC-DC BCM, and 4) DC-DC CCM. A low-frequency commutation scheme is also disclosed that allows for reducing the peak junction temperature.

Abstract: In circuitry for measuring a voltage at a node, a capacitive divider is coupled to the node, wherein the capacitive divider provides a first output. A resistive divider is coupled to the node, wherein the resistive divider provides a second output.

Abstract: The present disclosure provides electrical architecture for electrochemical impedance spectroscopy (EIS). An EIS circuit comprises at least two current regulators and an electrical energy storage device, which are connected with one or more electrochemical cells in a configuration that decouples power flowing into the respective current regulators. The presence of the electrical energy storage device enables each regulator to operate simultaneously at lower power levels while inducing the desired EIS perturbation current. Operation at low power allows lower volume and cost for the same current compared to only dissipative or non-dissipative current regulators. Further, the electrical energy storage device allows the power flowing through the current regulators to be varied independently in order to achieve the desired EIS perturbation current while a minimum amount of heat is generated in the circuit, thus allowing the circuit to occupy minimal size and incur minimal cost.

Abstract: A latch assembly for a closure panel and corresponding method of operation are provided. The assembly includes an actuation group to latch and unlatch the closure panel using power from a main power source during normal operation. A first backup energy source is selectively coupled to the actuation group and stores energy during normal operation and supplies the energy during a failure. A second backup energy source is selectively coupled to the first backup energy source and supplies energy thereto during the failure. A latch controller is coupled to the backup energy sources and detects latch operation and whether there is normal operation. The latch controller charges the first backup energy source using energy from the second backup energy source based on the detection of latch operation and the failure and disconnects the second backup energy source during normal operation to conserve energy stored in the second backup energy source.

Abstract: There are disclosed fault detection circuits and methods for an N-to-1 Dickson topology hybrid DC-DC power converter. A short circuit fault detection circuit comprises: first and second measuring circuits configured to measure first and second voltages, Vsw1, Vsw2, at the switching node in the first and second state; first and second calculation circuits configured to calculate first and second absolute error voltage as an absolute difference of the respective first and second voltages in one operating cycle (Vsw1[n?1], Vsw2[n?1]) and in a next subsequent operating cycle (Vsw1[n], Vsw2[n]); and first and second fault circuits configured to provide first and second fault outputs indicative of a fault in response to the respective first or second absolute error voltage exceeding a short-circuit-trip level. Open circuit fault detection circuits and methods are also disclosed.

Abstract: In an embodiment, a HEMT is formed to have a main transistor having a main active area and a sense transistor having a sense active area. An embodiment may include that the main active area is isolated from the sense active area.

Abstract: The present disclosure provides electrical architecture for electrochemical impedance spectroscopy (EIS). An EIS circuit comprises at least two current regulators and an electrical energy storage device, which are connected with one or more electrochemical cells in a configuration that decouples power flowing into the respective current regulators. The presence of the electrical energy storage device enables each regulator to operate simultaneously at lower power levels while inducing the desired EIS perturbation current. Operation at low power allows lower volume and cost for the same current compared to only dissipative or non-dissipative current regulators. Further, the electrical energy storage device allows the power flowing through the current regulators to be varied independently in order to achieve the desired EIS perturbation current while a minimum amount of heat is generated in the circuit, thus allowing the circuit to occupy minimal size and incur minimal cost.

Abstract: In circuitry for measuring a voltage at a node, a capacitive divider is coupled to the node, wherein the capacitive divider provides a first output. A resistive divider is coupled to the node, wherein the resistive divider provides a second output.

Abstract: Methods and circuitry for driving a device are disclosed. An example of the circuitry includes a voltage sensing circuit coupled to an input of a transistor, the voltage sensing circuit having a first output at a node, the voltage sensing circuit comprising a capacitive voltage divider, and a current sensing circuit coupled to the input of the transistor and to the voltage sensing circuit, the current sensing circuit having a second output, the current sensing circuit comprising a resistive divider coupled to the input of the transistor.

Abstract: Modern FPGAs operate at a core voltage around 1V and therefore even small voltage fluctuations can lead to timing violations and logic errors. The Power Delivery Network (PDN) between a power supply and the FPGA core must be carefully designed to achieve a low output impedance over a broad range of frequencies. The present disclosure describes two techniques for characterization of the PDN: 1) to extract the DC resistance in the power delivery path, and 2) to identify the high impedance frequency band(s) in the PDN. An embedded impedance extraction tool is synthesized within the FPGA load, in coordination with a mixed-signal current-mode dc-dc converter. A self-calibrated Carry-Chain based ADC (CC-ADC) is used for high-speed sampling of the core voltage. By modifying the PDN based on the extracted results, the voltage operating range and reliability of a crossbar application may be greatly extended.

Abstract: In circuitry for measuring a voltage at a node, a capacitive divider is coupled to the node, wherein the capacitive divider provides a first output. A resistive divider is coupled to the node, wherein the resistive divider provides a second output.

Abstract: Disclosed are switched-mode DC-DC power converter modules, SMPC controllers, and distributed-control multiphase SMPC systems. The controller comprises: a reference clock; a synchronisation input configured to receive a first synchronisation signal; a synchronisation output configured to transmit a second synchronisation signal; a control unit configured to control the operation of the SMPC module with a phase determined by the reference clock signal or the first synchronisation signal; a delay line configured to generate the second synchronisation signal by adding a delay to the selected one of the first synchronisation signal and the reference clock signal; a fault detection terminal; a memory configured to store a datum corresponding to a number N of SMPCs in the system; and a delay calculation module configured to calculate the delay in dependence on the datum and the signal at the fault-detection terminal. Associated methods are also disclosed.

Abstract: A power-hub for an electric vehicle and operating modes thereof are disclosed herein. The disclosed power-hub is designed to operate in the Vehicle-to Grid (V2G), Grid-to-Vehicle (G2V), Vehicle-to-Home (V2H), and Vehicle-to-Vehicle (V2V) operating modes. When operating in the V2V mode, the power-hub is configured to allow for sending DC power through a conventional AC power port, with all the associated ratings and constraints from the AC design, in order to achieve higher power transfer and efficiency for V2V operation. A digital Hysteretic Current Mode Control (HCMC) scheme is disclosed and the efficiency and loss distribution of four operating modes are disclosed for the power-hub: 1) DC-AC Boundary Conduction Mode (BCM), 2) DC-AC Continuous Conduction Mode (CCM)/BCM hybrid, 3) DC-DC BCM, and 4) DC-DC CCM. A low-frequency commutation scheme is also disclosed that allows for reducing the peak junction temperature.

Abstract: Methods and circuitry for driving a device are disclosed. An example of the circuitry includes a voltage sensing circuit coupled to an input of a transistor, the voltage sensing circuit having a first output at a node, the voltage sensing circuit comprising a capacitive voltage divider, and a current sensing circuit coupled to the input of the transistor and to the voltage sensing circuit, the current sensing circuit having a second output, the current sensing circuit comprising a resistive divider coupled to the input of the transistor.

Abstract: There are disclosed fault detection circuits and methods for an N-to-1 Dickson topology hybrid DC-DC power converter. A short circuit fault detection circuit comprises: first and second measuring circuits configured to measure first and second voltages, Vsw1, Vsw2, at the switching node in the first and second state; first and second calculation circuits configured to calculate first and second absolute error voltage as an absolute difference of the respective first and second voltages in one operating cycle (Vsw1[n?1], Vsw2[n?1]) and in a next subsequent operating cycle (Vsw1[n], Vsw2[n]); and first and second fault circuits configured to provide first and second fault outputs indicative of a fault in response to the respective first or second absolute error voltage exceeding a short-circuit-trip level. Open circuit fault detection circuits and methods are also disclosed.

Abstract: A DC-DC converter selectively operates in at least a first burst mode having at least one first-mode charge cycle with a first-mode charging phase followed by a first-mode discharging phase or a second burst mode having at least one second-mode charge cycle with a second-mode charging phase followed by a second-mode discharging phase. A first-mode charging phase is terminated when an inductor current flowing through the inductance reaches a first-mode peak-current threshold, and a first-mode discharging phase is terminated when the inductor current reaches a first-mode valley-current threshold.

Abstract: Disclosed are switched-mode DC-DC power converter modules, SMPC controllers, and distributed-control multiphase SMPC systems. The controller comprises: a reference clock; a synchronisation input configured to receive a first synchronisation signal; a synchronisation output configured to transmit a second synchronisation signal; a control unit configured to control the operation of the SMPC module with a phase determined by the reference clock signal or the first synchronisation signal; a delay line configured to generate the second synchronisation signal by adding a delay to the selected one of the first synchronisation signal and the reference clock signal; a fault detection terminal; a memory configured to store a datum corresponding to a number N of SMPCs in the system; and a delay calculation module configured to calculate the delay in dependence on the datum and the signal at the fault-detection terminal. Associated methods are also disclosed.