Abstract: Many digital processors have an asynchronous bus controlled by two control signals. To interface a synchronous memory to an asynchronous bus, interface logic is required. In an interface for transferring data from an asynchronous circuit to a synchronous circuit, data to be written are written in an intermediate register while timing control signals are being synchronized to a system clock by means of flip-flops. Correspondingly, in an interface for transferring data from the synchronous circuit to the asynchronous circuit, a signal indicating a read transaction from the synchronous circuit is synchronized to the system clock by means of a flip-flop circuit.

Abstract: A method and a receiver for forming transition metrics in the receiver of a digital cellular radio system. The receiver includes a hardware implementation of a transition metrics calculation unit for Viterbi decoding. The receiver includes a shift register for storing coefficients of a generator polynomial of a convolutional code. The receiver also includes masking means arranged to mask a state of the Viterbi decoding by the coefficients of the polynomial. The receiver has odd parity means arranged to form a parity bit of the state of the masked Viterbi decoding, the parity bit being arranged to control a block forming the transition metrics.

Abstract: A receiver and a method for determining connection quality in a cellular radio system. Received signals are decoded with a Viterbi decoder. Decision variables, representing decisions, are converted into a float value format. The converted decision variables are stored in a memory unit. During a traceback step of a Viterbi algorithm, a sum of absolute values of stored ones of the decision variables, which are in a correct path, are calculated and a minimum value of the absolute values of the stored ones of the decision variables in the correct path is calculated. The sum of the absolute values is averaged over a desired measurement period and compared to a predetermined threshold to obtain a bit error rate over a connection. Faulty signal frames are detected based on the minimum value of the absolute values.

Abstract: A method for testing an integrated circuit that has a testing portion for testing the circuit card and/or other circuits connected to the integrated circuit after the integrated circuit has been assembled onto the circuit card, inputs for controlling the testing portion, and test structures for testing the internal operations of the integrated circuit. To keep the number of the inputs to the circuit low, a test mode is defined for the testing portion, in which test mode one of the inputs of the testing portion is connected to the test structures for the internal operations of the integrated circuit, and when the internal operations of the integrated circuit are tested, the testing portion is set in the test mode, whereupon the internal test structures of the integrated circuit can be controlled from the input of the testing portion.