Abstract: A clock signal polarity controlling circuit comprises a first latch comprising a clock input, a data input and an output. The data input is coupled to an output of a clock signal generator, the clock input is coupled to a reference clock signal. The clock signal polarity controlling circuit further comprises a second latch comprising a clock input, a data input and an output. The data input is coupled to the output of the first latch, the clock input is coupled to the reference clock signal. The circuit further comprises an XOR circuit comprising a first and second inputs and an output. The first and second inputs are coupled to the output of the second latch and the output of the clock signal generator respectively, and a clock signal having a polarity controlled by the reference clock signal is generated at the output of the XOR circuit.

Abstract: A clock signal polarity controlling circuit comprises a first latch comprising a clock input, a data input and an output. The data input is coupled to an output of a clock signal generator, the clock input is coupled to a reference clock signal. The clock signal polarity controlling circuit further comprises a second latch comprising a clock input, a data input and an output. The data input is coupled to the output of the first latch, the clock input is coupled to the reference clock signal. The circuit further comprises an XOR circuit comprising a first and second inputs and an output. The first and second inputs are coupled to the output of the second latch and the output of the clock signal generator respectively, and a clock signal having a polarity controlled by the reference clock signal is generated at the output of the XOR circuit.

Abstract: The invention discloses an RF ASIC, (100), which comprises first (110) and second (130) plane conductors arranged parallel to each other with an isolating material (120) of a certain thickness (d) between them, and a ground plane (150) arranged in parallel to said conductors and at a certain distance (h) from the nearest conductor. Each conductor (110, 130) is shaped as a rectangle with a width (W) and a length (L) such that the length exceeds the width, so that each conductor has opposing short sides and opposing long sides. Each conductor exhibits a connector (1, 2, 3, 4) at each of its short sides, and the ASIC can be used as a transformer by using the connectors (1, 2) on one opposing short side as input ports to the transformer, and the connectors (3, 4) on the other opposing short side as output ports.