Abstract: A sampling device samples a differential measuring voltage. The sampling device comprises a first holding device, a second holding device and a multiplexing circuit, which is configured to provide a differential sample of a sampled differential signal, derived from the differential measuring voltage by sampling with a first clock signal of a first clock rate, to the first holding device, at the occurrence of each HIGH-value of a second clock signal of a second clock rate being half of the first clock rate and provide a differential sample of the sample differential signal to the second holding device, at each LOW-value of the second clock signal. The sampling device comprises a reset device configured to reset the second holding device at or after each HIGH-value of the second clock signal and reset the first holding device at or after each LOW-value of the second clock signal.

Abstract: A delay line device is provided for a high frequency sampler for high frequency signal transmission, or for an oscilloscope for measuring high frequency signals. The delay line device includes two distributed tapped transmission delay lines. Each of the delay lines includes two terminals. An analog input signal is applied to a first terminal of the first delay line, and a clock signal is applied to a first terminal of the second delay line. The delay lines are configured such that the analog input signal propagates through the first delay line in an opposite direction as compared to the propagation of the clock signal through the second delay line.

Abstract: In order to further develop a circuit arrangement (CR; CR?) for receiving optical signals (SI) from at least one optical guide (GU), said circuit arrangement (CR; CR?) comprising: at least one light-receiving component (PD) for converting the optical signals (SI) into electrical current signals (IPD), at least one transimpedance amplifier (TA), being provided with the electrical current signals (IPD) from the light-receiving component (PD), at least one automatic gain controller (AG) for controlling the gain or transimpedance (R) of the transimpedance amplifier (TA), at least one integrator (IN) in a feedback path (FP), said integrator (IN) generating a control signal (Vint), at least one voltage-controlled current source (CS), being provided with the control signal (Vint) from the integrator (IN), at least one limiter (LI) acting as a comparator and generating in its output a logic level for positive or negative voltages in its input, and a corresponding method in such a way that a multilevel optical lin

Abstract: A sampling device samples a differential measuring voltage. The sampling device comprises a first holding device, a second holding device and a multiplexing circuit, which is configured to provide a differential sample of a sampled differential signal, derived from the differential measuring voltage by sampling with a first clock signal of a first clock rate, to the first holding device, at the occurrence of each HIGH-value of a second clock signal of a second clock rate being half of the first clock rate and provide a differential sample of the sample differential signal to the second holding device, at each LOW-value of the second clock signal. The sampling device comprises a reset device configured to reset the second holding device at or after each HIGH-value of the second clock signal and reset the first holding device at or after each LOW-value of the second clock signal.

Abstract: A delay line system for high frequency signal transmission comprises a first delay line and a second delay line that are each tapped. The first delay line comprises a first terminal and a second terminal, and the second delay line comprises a first terminal and a second terminal. The first delay line and the second delay line are configured in a manner whereby an analog input signal applied to the first terminal of the first delay line propagates through the first delay line in a first direction, a clock signal applied to the first terminal of the second delay line propagates through the second delay line in a second direction, and the first direction is opposite to the second direction. Further, an oscilloscope for measuring high frequency signals comprises an ADC, which comprises a high frequency sampler, which comprises such a delay line system.

Abstract: In order to further develop a circuit arrangement (CR; CR?) for receiving optical signals (SI) from at least one optical guide (GU), said circuit arrangement (CR; CR?) comprising: at least one light-receiving component (PD) for converting the optical signals (SI) into electrical current signals (IPD), at least one transimpedance amplifier (TA), being provided with the electrical current signals (IPD) from the light-receiving component (PD), at least one automatic gain controller (AG) for controlling the gain or transimpedance (R) of the transimpedance amplifier (TA), at least one integrator (IN) in a feedback path (FP), said integrator (IN) generating a control signal (Vint), at least one voltage-controlled current source (CS), being provided with the control signal (Vint) from the integrator (IN), at least one limiter (LI) acting as a comparator and generating in its output a logic level for positive or negative voltages in its input, and a corresponding method in such a way that a multilevel optical link

Abstract: An integrated circuit requires on-chip termination resistor for minimizing reflections from input signals supplied by an external signal source. The input signal is applied across two bonding pads which serve as input terminals for the integrated circuit. The first bonding pad is coupled to a first on-chip terminating resistor through a first on-chip inductor. The second bonding pad is coupled to a second on-chip terminating resistor though a second on-chip inductor. The two on-chip inductors are arranged in a transformer configuration where the mutual inductance relative to the applied input signal is negative. During operation, the on-chip transformer arrangement effectively shorts common-mode signals to the on-chip terminating resistors and effectively blocks differential-mode signals from the on-chip terminating resistors. Effective bandwidth and common-mode rejection performance is improved with the described on-chip transformer arrangement.

Abstract: A track/hold circuit with an offset adjustment that can be used to compensate for offset errors from other parts of the system containing the track/hold circuit. The offset adjustment may be provided by impressing a voltage at an electrode of a capacitor of the track/hold circuit during a hold mode and not impressing the voltage at the capacitor electrode during the track mode. The offset adjustment signal may be generated using an adjustable current source to propagate a current through a resistance that is coupled to the track/hold circuit output node via a capacitor of a voltage capacitive divider circuit during the hold mode. The offset introduced into the track/hold mode output signal can be independent of the voltage stored in the voltage capacitive divider circuit just prior to adding the offset adjustment signal.

Abstract: A reference voltage is generated between a first node and a second node. A resistive element and a junction device are coupled in series between the first node and the second node. The junction device includes a junction between dissimilar materials, and has a negative temperature coefficient. First and second current sources route respective first and second bias currents to the resistive element and to the junction device. Routing is such that a resulting first branch current through the resistive element is generally not equal to a resulting second branch current through the junction device. The second bias current depends less on manufacturing process variation than the first bias current, and the second branch current can contain more of it, for less dependence on process. The second bias current can be generated by a source that uses the generated reference voltage as a reference.

Abstract: An ADC circuit includes a multiplexer, a calibration circuit, one or more ADC banks, and a calibration ladder, all on an integrated circuit. The calibration resistor ladder is enabled during a calibration phase, and disabled during normal operation. When enabled, the calibration resistor ladder provides a calibration reference signal. Also, the multiplexer provides the calibration reference signal to one or more ADC banks during a calibration phase, and provides an analog input signal to the ADC banks otherwise. The calibration circuit is arranged to provide one or more adjustment signals to the ADC banks to calibrate the ADC banks in response to one or more comparator output signals from the ADC banks.