Patents by Inventor Oluwafemi O. Ogunsola

Oluwafemi O. Ogunsola has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170170016
    Abstract: Methods for multiple patterning a substrate may include: forming a hard mask including a carbonaceous layer and an oxynitride layer over the carbonaceous layer on a substrate; and forming a first pattern into the oxynitride layer and partially into the carbonaceous layer using a first soft mask positioned over the hard mask. A wet etching removes a portion of the first soft mask from the first pattern in the oxynitride layer without damaging the carbonaceous layer. Subsequently, a second pattern and a third pattern are formed into the hard mask, creating a multiple pattern in the hard mask. The multiple pattern may be etched into the substrate, followed by removing any remaining portion of the hard mask.
    Type: Application
    Filed: December 14, 2015
    Publication date: June 15, 2017
    Inventors: Woo-Hyeong Lee, Jujin An, Shahrukh A. Khan, Rosa A. Orozco-Teran, Oluwafemi O. Ogunsola, William K. Henson, Scott R. Stiffler
  • Patent number: 9087803
    Abstract: Methods of fabricating integrated circuit devices utilize fuse elements to support sequential testing of vertically-integrated test elements during fabrication. These methods include forming a first test element, a first fuse and a first test pad electrically connected by the first fuse to the first test element, on a substrate. The first test element is tested by passing a first current between the first test element and first test pad and through the first fuse. The first fuse is then “cut” by increasing an impedance of the first fuse, which may include breaking the first fuse to create an electrical “open” (infinite impedance) or greatly increasing a resistance of the first fuse (e.g., by narrowing the fuse through electromigration). A second test element and a second test pad, which is electrically connected to the second test element and the first test pad, are then formed on the substrate.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: July 21, 2015
    Assignees: Samsung Electronics Co., Ltd., International Business Machines Corporation
    Inventors: Jeong-Hoon Ahn, Hyun-Min Choi, Oluwafemi O. Ogunsola
  • Patent number: 8822342
    Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: September 2, 2014
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Ravi Prakash Srivastava, Oluwafemi. O. Ogunsola, Craig Child, Muhammed Shafi Kurikka Valappil Pallachalil, Habib Hichri, Matthew Angyal, Hideshi Miyajima
  • Patent number: 8450212
    Abstract: A method including forming an organic polymer layer (OPL) on a substrate; forming a patterned photoresist layer having a first opening and a second opening over the OPL, the second opening wider than the first opening; performing a first reactive ion etch (RIE) to form a first trench and a second trench in the organic layer, the second trench wider than the first trench, the first trench extending into but not through the organic polymer layer, the second trench extending through the OPL to the substrate, the first RIE forming a first polymer layer on sidewalls of the first trench and a second polymer layer on sidewalls of the second trench, the second polymer layer thicker than the first polymer layer; and performing a second RIE to extend the first trench through the OPL to the substrate, the second RIE removing the second polymer layer from sidewalls of the second trench.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: May 28, 2013
    Assignee: International Business Machines Corporation
    Inventors: Matthew S. Angyal, Oluwafemi O. Ogunsola, Hakeem B. Akinmade-Yusuff
  • Publication number: 20130130415
    Abstract: Methods of fabricating integrated circuit devices utilize fuse elements to support sequential testing of vertically-integrated test elements during fabrication. These methods include forming a first test element, a first fuse and a first test pad electrically connected by the first fuse to the first test element, on a substrate. The first test element is tested by passing a first current between the first test element and first test pad and through the first fuse. The first fuse is then “cut” by increasing an impedance of the first fuse, which may include breaking the first fuse to create an electrical “open” (infinite impedance) or greatly increasing a resistance of the first fuse (e.g., by narrowing the fuse through electromigration). A second test element and a second test pad, which is electrically connected to the second test element and the first test pad, are then formed on the substrate.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 23, 2013
    Inventors: Jeong-Hoon AHN, Hyun-Min Choi, Oluwafemi O. Ogunsola
  • Publication number: 20130005147
    Abstract: A method including forming an organic polymer layer (OPL) on a substrate; forming a patterned photoresist layer having a first opening and a second opening over the OPL, the second opening wider than the first opening; performing a first reactive ion etch (RIE) to form a first trench and a second trench in the organic layer, the second trench wider than the first trench, the first trench extending into but not through the organic polymer layer, the second trench extending through the OPL to the substrate, the first RIE forming a first polymer layer on sidewalls of the first trench and a second polymer layer on sidewalls of the second trench, the second polymer layer thicker than the first polymer layer; and performing a second RIE to extend the first trench through the OPL to the substrate, the second RIE removing the second polymer layer from sidewalls of the second trench.
    Type: Application
    Filed: June 28, 2011
    Publication date: January 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew S. Angyal, Oluwafemi O. Ogunsola, Hakeem B. Akinmade-Yusuff
  • Publication number: 20120168957
    Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.
    Type: Application
    Filed: December 30, 2010
    Publication date: July 5, 2012
    Applicants: GLOBALFOUNDRIES SINGAPORE PTE. LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION, TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC., INFINEON TECHNOLOGIES NORTH AMERICA CORP., ADVANCED MICRO DEVICES CORPORATION
    Inventors: Ravi Prakash SRIVASTAVA, Oluwafemi O. OGUNSOLA, Craig CHILD, Muhammed Shafi Kurikka Valappil PALLACHALIL, Habib HICHRI, Matthew ANGYAL, Hideshi MIYAJIMA
  • Patent number: 7348786
    Abstract: Probe modules, methods of use of probe modules, and methods of preparing probe modules, are disclosed. A representative embodiment of a probe module, among others, includes a redistribution substrate and a probe substrate interfaced with the redistribution substrate. The probe substrate is operative to test at least one signal of at least one optoelectronic device under test. The probe substrate is operative to interface with electrical and optical components.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: March 25, 2008
    Assignee: Georgia Tech Research Corporation
    Inventors: Hiren D. Thacker, Oluwafemi O. Ogunsola, James D. Meindl
  • Patent number: 7099528
    Abstract: Diffractive optical elements are used in methods and devices for coupling or distributing electromagnetic radiation. The diffractive optical. elements may be adapted to split one or more streams of radiation into multiple streams of radiation or to combine multiple streams of radiation to produce single streams. A plurality of diffractive optical elements may be fabricated on substrates by lithographic or molding methods. Diffractive optical elements that split one or more streams of radiation can be combined with diffractive optical elements that combine multiple streams of radiation to provide a coupling device, for example, a star coupler. The star coupler may be used in networked optical communication systems to provide multiple coupling between a plurality of optical drivers and a plurality of optical receivers. Aspects can be applied to any type of electromagnetic radiation having a wavelength that can be used as a medium for transferring information.
    Type: Grant
    Filed: January 7, 2004
    Date of Patent: August 29, 2006
    Assignee: International Business Machines Corporation
    Inventors: Alan F. Benner, Oluwafemi O. Ogunsola