Patents by Inventor Oluwatobi A. Ajila

Oluwatobi A. Ajila has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240069944
    Abstract: Aspects of the invention include systems and methods configured to checkpoint an application executing on a virtual machine. Aspects include receiving from a first thread executing on a virtual machine a call to a checkpoint application program interface (API) and suspending, by the virtual machine, execution of all threads other than the first thread. Aspects also includes executing, by the virtual machine, all application checkpoint hooks and executing, by the virtual machine, all virtual machine checkpoint hooks. Aspects further include creating one or more checkpoint image files.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Inventors: Oluwatobi Ajila, Vijay Sundaresan, Thomas J. Watson, Daniel Heidinga
  • Patent number: 11662983
    Abstract: A computer-implemented method for bytecode class verification includes: encountering a class requiring verification of its bytecode during a run of an application; determining whether class relationship data for the class exists in a shared classes cache; in response to a determination that the class relationship data for the class does not exist in the shared classes cache: performing a linear bytecode walk of the bytecode to identify relationship data for the class and verify that the bytecode is well-formed; and storing the identified relationship data as the class relationship data for the class in the shared classes cache; in response to a determination that the class relationship data for the class does exist in the shared classes cache: retrieving the class relationship data for the class from the shared classes cache; and processing the class relationship data.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: May 30, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sharon Wang, Daniel Heidinga, Hang Shao, Oluwatobi Ajila, Graham Chapman
  • Patent number: 11656888
    Abstract: A snapshot handler is registered with an event monitoring subsystem of a process virtual machine, the registering specifying a trigger event of the snapshot handler, wherein the trigger event comprises execution of a specified portion of an application executing in the process virtual machine, the trigger event specified externally from a source code of the application. Responsive to the event monitoring subsystem detecting an occurrence of the trigger event, the snapshot handler is executed, storing data of an execution state of the process virtual machine at a time of occurrence of the trigger event.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: May 23, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oluwatobi Ajila, Daniel Heidinga
  • Publication number: 20220382576
    Abstract: A snapshot handler is registered with an event monitoring subsystem of a process virtual machine, the registering specifying a trigger event of the snapshot handler, wherein the trigger event comprises execution of a specified portion of an application executing in the process virtual machine, the trigger event specified externally from a source code of the application. Responsive to the event monitoring subsystem detecting an occurrence of the trigger event, the snapshot handler is executed, storing data of an execution state of the process virtual machine at a time of occurrence of the trigger event.
    Type: Application
    Filed: August 8, 2022
    Publication date: December 1, 2022
    Applicant: International Business Machines Corporation
    Inventors: Oluwatobi Ajila, DANIEL HEIDINGA
  • Patent number: 11500661
    Abstract: A snapshot handler is registered with an event monitoring subsystem of a process virtual machine, the registering specifying a trigger event of the snapshot handler, wherein the trigger event comprises execution of a specified portion of an application executing in the process virtual machine, the trigger event specified externally from a source code of the application. Responsive to the event monitoring subsystem detecting an occurrence of the trigger event, the snapshot handler is executed, storing data of an execution state of the process virtual machine at a time of occurrence of the trigger event.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: November 15, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oluwatobi Ajila, Daniel Heidinga
  • Publication number: 20220283785
    Abstract: A computer-implemented method for bytecode class verification includes: encountering a class requiring verification of its bytecode during a run of an application; determining whether class relationship data for the class exists in a shared classes cache; in response to a determination that the class relationship data for the class does not exist in the shared classes cache: performing a linear bytecode walk of the bytecode to identify relationship data for the class and verify that the bytecode is well-formed; and storing the identified relationship data as the class relationship data for the class in the shared classes cache; in response to a determination that the class relationship data for the class does exist in the shared classes cache: retrieving the class relationship data for the class from the shared classes cache; and processing the class relationship data.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 8, 2022
    Inventors: Sharon WANG, Daniel HEIDINGA, Hang SHAO, Oluwatobi AJILA, Graham CHAPMAN
  • Patent number: 11403075
    Abstract: A computer-implemented method for bytecode class verification includes: encountering a class requiring verification of its bytecode during a run of an application; determining whether class relationship data for the class exists in a shared classes cache; in response to a determination that the class relationship data for the class does not exist in the shared classes cache: performing a linear bytecode walk of the bytecode to identify relationship data for the class and verify that the bytecode is well-formed; and storing the identified relationship data as the class relationship data for the class in the shared classes cache; in response to a determination that the class relationship data for the class does exist in the shared classes cache: retrieving the class relationship data for the class from the shared classes cache; and processing the class relationship data.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: August 2, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sharon Wang, Daniel Heidinga, Hang Shao, Oluwatobi Ajila, Graham Chapman
  • Publication number: 20220066805
    Abstract: A snapshot handler is registered with an event monitoring subsystem of a process virtual machine, the registering specifying a trigger event of the snapshot handler, wherein the trigger event comprises execution of a specified portion of an application executing in the process virtual machine, the trigger event specified externally from a source code of the application. Responsive to the event monitoring subsystem detecting an occurrence of the trigger event, the snapshot handler is executed, storing data of an execution state of the process virtual machine at a time of occurrence of the trigger event.
    Type: Application
    Filed: August 26, 2020
    Publication date: March 3, 2022
    Applicant: International Business Machines Corporation
    Inventors: Oluwatobi Ajila, Daniel Heidinga
  • Patent number: 11221867
    Abstract: Resolving segmented constant pools in a virtual machine managed runtime. An embodiment includes allocating, using one or more processors of a computing device, for each specialization created in a class of specializations, a constant pool (CP) cache, assigning an owner to each segment of constant pools, maintaining, in a memory of the computing device, a list of specializations in the class, and copying, upon determining that a CP segment entry visible to the specialization is resolved in the owner, the entry to a specializations cache of the memory. An embodiment includes assigning a new specialized CP segment as an owner of that CP segment and adding a new entry associated with the new specialization to a template class owners table, retrieving, based on looking for entry at runtime, a slot pointed to in the owners table and resolving the CP entry in the constant pool cache of the owner.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: January 11, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oluwatobi Ajila, Daniel Heidinga
  • Patent number: 11188316
    Abstract: An embodiment includes executing a code interpretation engine such that the interpretation engine interprets a first portion of a source code that includes a first comparison between a first pair of operands. The embodiment also includes performing, in memory, a first bitwise comparison between a block A1 and a block B1 of the first portion of the source code. The embodiment also speeds up execution of the first portion of the source code responsive to the first bitwise comparison producing a negative result. The embodiment speeds up the first portion by omitting at least one of (i) a second bitwise comparison between a block A2 and a block B2, and (ii) a field-wise comparison between a block A3 and a block B3.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: November 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oluwatobi Ajila, Andrew James Craik, Daniel Heidinga, Graham Alan Chapman
  • Publication number: 20210279044
    Abstract: An embodiment includes executing a code interpretation engine such that the interpretation engine interprets a first portion of a source code that includes a first comparison between a first pair of operands. The embodiment also includes performing, in memory, a first bitwise comparison between a block A1 and a block B1 of the first portion of the source code. The embodiment also speeds up execution of the first portion of the source code responsive to the first bitwise comparison producing a negative result. The embodiment speeds up the first portion by omitting at least one of (i) a second bitwise comparison between a block A2 and a block B2, and (ii) a field-wise comparison between a block A3 and a block B3.
    Type: Application
    Filed: March 9, 2020
    Publication date: September 9, 2021
    Applicant: International Business Machines Corporation
    Inventors: Oluwatobi Ajila, Andrew James Craik, Daniel Heidinga, Graham Alan Chapman
  • Publication number: 20210208914
    Abstract: Resolving segmented constant pools in a virtual machine managed runtime. An embodiment includes allocating, using one or more processors of a computing device, for each specialization created in a class of specializations, a constant pool (CP) cache, assigning an owner to each segment of constant pools, maintaining, in a memory of the computing device, a list of specializations in the class, and copying, upon determining that a CP segment entry visible to the specialization is resolved in the owner, the entry to a specializations cache of the memory. An embodiment includes assigning a new specialized CP segment as an owner of that CP segment and adding a new entry associated with the new specialization to a template class owners table, retrieving, based on looking for entry at runtime, a slot pointed to in the owners table and resolving the CP entry in the constant pool cache of the owner.
    Type: Application
    Filed: January 2, 2020
    Publication date: July 8, 2021
    Applicant: International Business Machines Corporation
    Inventors: Oluwatobi Ajila, daniel Heidinga
  • Publication number: 20210157552
    Abstract: A computer-implemented method for bytecode class verification includes: encountering a class requiring verification of its bytecode during a run of an application; determining whether class relationship data for the class exists in a shared classes cache; in response to a determination that the class relationship data for the class does not exist in the shared classes cache: performing a linear bytecode walk of the bytecode to identify relationship data for the class and verify that the bytecode is well-formed; and storing the identified relationship data as the class relationship data for the class in the shared classes cache; in response to a determination that the class relationship data for the class does exist in the shared classes cache: retrieving the class relationship data for the class from the shared classes cache; and processing the class relationship data.
    Type: Application
    Filed: November 25, 2019
    Publication date: May 27, 2021
    Inventors: Sharon WANG, Daniel HEIDINGA, Hang SHAO, Oluwatobi AJILA, Graham CHAPMAN
  • Patent number: 10678482
    Abstract: Aspects provide multi-tier data synchronization based on a concurrent linked monitor list. A computer processor associates each of different data regions of a packed data object with different mutual exclusion monitor nodes of a linked list, the data regions defined by a data offset location within memory data and a length of the data region from the offset. In response to determining that a first data region of the packed data object is on-heap memory, the processor associates the first data region with a container representative of the linked list sorted in ascending order of the respective offset values, and a hash code of the container; and in response to determining that a second data region of the packed data object is off-heap memory, stores container information for the second data region in the linked list and resorts the linked-list nodes of container information in ascending order of offset values.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Oluwatobi A. Ajila, Eric Aubanel, Kenneth B. Kent, Angela Lin, Bing Yang
  • Publication number: 20180329641
    Abstract: Aspects provide multi-tier data synchronization based on a concurrent linked monitor list. A computer processor associates each of different data regions of a packed data object with different mutual exclusion monitor nodes of a linked list, the data regions defined by a data offset location within memory data and a length of the data region from the offset. In response to determining that a first data region of the packed data object is on-heap memory, the processor associates the first data region with a container representative of the linked list sorted in ascending order of the respective offset values, and a hash code of the container; and in response to determining that a second data region of the packed data object is off-heap memory, stores container information for the second data region in the linked list and resorts the linked-list nodes of container information in ascending order of offset values.
    Type: Application
    Filed: July 24, 2018
    Publication date: November 15, 2018
    Inventors: OLUWATOBI A. AJILA, Eric Aubanel, Kenneth B. Kent, Angela Lin, Bing Yang
  • Patent number: 10073646
    Abstract: Aspects provide multi-tier data synchronization based on a concurrent linked monitor list. A computer processor associates each of different data regions of a packed data object with different mutual exclusion monitor nodes of a linked list, the data regions defined by a data offset location within memory data and a length of the data region from the offset. In response to determining that a first data region of the packed data object is on-heap memory, the processor associates the first data region with a container representative of the linked list sorted in ascending order of the respective offset values, and a hash code of the container; and in response to determining that a second data region of the packed data object is off-heap memory, stores container information for the second data region in the linked list and resorts the linked-list nodes of container information in ascending order of offset values.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Oluwatobi A. Ajila, Eric Aubanel, Kenneth B. Kent, Angela Lin, Bing Yang
  • Patent number: 10061570
    Abstract: In an approach for removing tenant initialization check per tenant for compiled code, a processor receives a request to create a tenant. A processor creates the tenant. A processor marks a current thread of the tenant as not eligible to run just-in-time (JIT) code, wherein the marking indicates that when a method is invoked, a non-JIT version of the method is executed. A processor executes initialization of a first class from an optimization list, wherein the optimization list is a configurable list of classes to be initialized prior to running JIT code. A processor determines that class initialization has been executed for all classes on the optimization list. A processor adjusts the marking to indicate that the current thread is eligible to run JIT code and that the tenant may run JIT code that assumes, without checking, that classes on the optimization list are initialized.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 28, 2018
    Assignee: International Business Machines Corporation
    Inventors: Oluwatobi A. Ajila, Graham A. Chapman, Michael H. Dawson, San Hong Li, Hui Shi
  • Publication number: 20180217776
    Abstract: Aspects provide multi-tier data synchronization based on a concurrent linked monitor list. A computer processor associates each of different data regions of a packed data object with different mutual exclusion monitor nodes of a linked list, the data regions defined by a data offset location within memory data and a length of the data region from the offset. In response to determining that a first data region of the packed data object is on-heap memory, the processor associates the first data region with a container representative of the linked list sorted in ascending order of the respective offset values, and a hash code of the container; and in response to determining that a second data region of the packed data object is off-heap memory, stores container information for the second data region in the linked list and resorts the linked-list nodes of container information in ascending order of offset values.
    Type: Application
    Filed: January 31, 2017
    Publication date: August 2, 2018
    Inventors: OLUWATOBI A. AJILA, ERIC AUBANEL, ANGELA LIN, KENNETH B. KENT, BING YANG
  • Publication number: 20180203853
    Abstract: A method, computer program product, and system includes a processor(s) generating an interface to enable communication of data elements from a first computing resource to a second computing resource. An element of the data is a data structure of variable size. To generate the interface, the processor(s) requests a layout that includes a variable array. The processor(s) locates a layout referenced by the variable array; the layout for the variable array can accommodate the data structure of variable size. The processor(s) generates the layout, which includes generating a runtime class for an element type of the data structure of variable size and generating a runtime class for the variable array. The processor generates an enclosing layout that indicates to the second computing resource, delineations between the data elements. The processor(s) communicates, via the interface, the data elements from the first computing resource to the second computing resource.
    Type: Application
    Filed: January 13, 2017
    Publication date: July 19, 2018
    Inventors: Oluwatobi A. AJILA, Daniel J. HEIDINGA
  • Publication number: 20170017474
    Abstract: In an approach for removing tenant initialization check per tenant for compiled code, a processor receives a request to create a tenant. A processor creates the tenant. A processor marks a current thread of the tenant as not eligible to run just-in-time (JIT) code, wherein the marking indicates that when a method is invoked, a non-JIT version of the method is executed. A processor executes initialization of a first class from an optimization list, wherein the optimization list is a configurable list of classes to be initialized prior to running JIT code. A processor determines that class initialization has been executed for all classes on the optimization list. A processor adjusts the marking to indicate that the current thread is eligible to run JIT code and that the tenant may run JIT code that assumes, without checking, that classes on the optimization list are initialized.
    Type: Application
    Filed: September 30, 2016
    Publication date: January 19, 2017
    Inventors: Oluwatobi A. Ajila, Graham A. Chapman, Michael H. Dawson, San Hong Li, Hui Shi