Patents by Inventor Om Ranjan
Om Ranjan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11822934Abstract: A processing system includes a plurality of configuration data clients; each associated with a respective address and including a respective register, a hardware block, a non-volatile memory, and a hardware configuration circuit. A respective configuration data client receives a respective first configuration data and stores it in the respective register. The hardware block is coupled to at least one of the configuration data clients and changes operation as a function of the respective first configuration data stored in the respective registers. The non-volatile memory includes second configuration data stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients. The hardware configuration circuit sequentially reads the data packets from the non-volatile memory and transmits the respective first configuration data to the respective configuration data client.Type: GrantFiled: June 7, 2021Date of Patent: November 21, 2023Assignees: STMicroelectronics Application GMBH, STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Roberto Colombo, Om Ranjan
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Patent number: 11436162Abstract: A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.Type: GrantFiled: May 22, 2020Date of Patent: September 6, 2022Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics S.r.l., STMicroelectronics International N.V.Inventors: Riccardo Gemelli, Denis Dutey, Om Ranjan
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Publication number: 20210294534Abstract: A processing system includes a plurality of configuration data clients, each associated with a respective address and including a respective register, and where a respective configuration data client is configured to receive a respective first configuration data and to store the respective first configuration data in the respective register; a hardware block coupled to at least one of the configuration data clients and configured to change operation as a function of the respective first configuration data stored in the respective registers; a non-volatile memory including second configuration data, where the second configuration data are stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients; and a hardware configuration circuit configured to sequentially read the data packets from the non-volatile memory and to transmit the respective first configuration data to the respective configuration daType: ApplicationFiled: June 7, 2021Publication date: September 23, 2021Inventors: Roberto Colombo, Om Ranjan
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Patent number: 11055173Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.Type: GrantFiled: December 4, 2019Date of Patent: July 6, 2021Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics International N.V., STMicroelectronics S.r.l.Inventors: Om Ranjan, Riccardo Gemelli, Denis Dutey
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Patent number: 11048525Abstract: A processing system includes a plurality of configuration data clients, each associated with a respective address and including a respective register, and where a respective configuration data client is configured to receive a respective first configuration data and to store the respective first configuration data in the respective register; a hardware block coupled to at least one of the configuration data clients and configured to change operation as a function of the respective first configuration data stored in the respective registers; a non-volatile memory including second configuration data, where the second configuration data are stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients; and a hardware configuration circuit configured to sequentially read the data packets from the non-volatile memory and to transmit the respective first configuration data to the respective configuration daType: GrantFiled: February 12, 2019Date of Patent: June 29, 2021Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS APPLICATION GMBHInventors: Roberto Colombo, Om Ranjan
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Patent number: 10860415Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.Type: GrantFiled: June 27, 2019Date of Patent: December 8, 2020Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.Inventors: Om Ranjan, Riccardo Gemelli, Abhishek Gupta
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Publication number: 20200379924Abstract: A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.Type: ApplicationFiled: May 22, 2020Publication date: December 3, 2020Inventors: Riccardo Gemelli, Denis Dutey, Om Ranjan
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Publication number: 20200110663Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.Type: ApplicationFiled: December 4, 2019Publication date: April 9, 2020Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics International N.V., STMicroelectronics S.r.l.Inventors: Om RANJAN, Riccardo GEMELLI, Denis DUTEY
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Patent number: 10528422Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.Type: GrantFiled: November 13, 2017Date of Patent: January 7, 2020Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l., STMicroelectronics (Grenoble 2) SASInventors: Om Ranjan, Riccardo Gemelli, Denis Dutey
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Publication number: 20190317851Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.Type: ApplicationFiled: June 27, 2019Publication date: October 17, 2019Applicants: STMicroelectronics International N.V., STMicroelectronics S.r.l.Inventors: Om RANJAN, Riccardo GEMELLI, Abhishek GUPTA
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Publication number: 20190258493Abstract: A processing system includes a plurality of configuration data clients, each associated with a respective address and including a respective register, and where a respective configuration data client is configured to receive a respective first configuration data and to store the respective first configuration data in the respective register; a hardware block coupled to at least one of the configuration data clients and configured to change operation as a function of the respective first configuration data stored in the respective registers; a non-volatile memory including second configuration data, where the second configuration data are stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients; and a hardware configuration circuit configured to sequentially read the data packets from the non-volatile memory and to transmit the respective first configuration data to the respective configuration daType: ApplicationFiled: February 12, 2019Publication date: August 22, 2019Inventors: Roberto Colombo, Om RANJAN
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Patent number: 10379937Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.Type: GrantFiled: October 31, 2017Date of Patent: August 13, 2019Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.Inventors: Om Ranjan, Riccardo Gemelli, Abhishek Gupta
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Publication number: 20190146868Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.Type: ApplicationFiled: November 13, 2017Publication date: May 16, 2019Applicants: STMicroelectronics International N.V., STMicroelectronics S.r.l., STMicroelectronics (Crolles 2) SASInventors: Om Ranjan, Riccardo Gemelli, Denis Dutey
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Publication number: 20190129790Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.Type: ApplicationFiled: October 31, 2017Publication date: May 2, 2019Applicants: STMicroelectronics International N.V., STMicroelectronics S.r.l.Inventors: Om Ranjan, Riccardo Gemelli, Abhishek Gupta
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Patent number: 9990245Abstract: An electronic device includes a memory having memory locations being subject to transient faults and permanent faults, and a fault detection circuit coupled to the memory. The fault detection circuit is configured to read the memory locations at a first time, and determine a first fault count and fault map signature including the transient and permanent faults at the first time based upon reading the plurality of memory locations, and to store the first fault count and fault map signature. The fault detection circuit is configured to read the memory locations at a second time and determine a second fault count and fault map signature including the transient and permanent faults at the second time based upon reading the memory locations, and compare the stored first fault count and fault map signature with the second fault count and fault map signature to determine a permanent fault count.Type: GrantFiled: November 25, 2015Date of Patent: June 5, 2018Assignees: STMicroelectronics S.r.l., STMicroelectronics International N.V.Inventors: Om Ranjan, Fabio Enrico Carlo Disegni
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Publication number: 20170147416Abstract: An electronic device includes a memory having memory locations being subject to transient faults and permanent faults, and a fault detection circuit coupled to the memory. The fault detection circuit is configured to read the memory locations at a first time, and determine a first fault count and fault map signature including the transient and permanent faults at the first time based upon reading the plurality of memory locations, and to store the first fault count and fault map signature. The fault detection circuit is configured to read the memory locations at a second time and determine a second fault count and fault map signature including the transient and permanent faults at the second time based upon reading the memory locations, and compare the stored first fault count and fault map signature with the second fault count and fault map signature to determine a permanent fault count.Type: ApplicationFiled: November 25, 2015Publication date: May 25, 2017Inventors: Om RANJAN, Fabio Enrico Carlo DISEGNI
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Patent number: 9558052Abstract: A safety system monitors faults in an embedded control system. The embedded control system is modeled to produce one or more model check values by calculating how many clock cycles will pass between an initialization time point and at least one event time point for a specific event. The initialization time point is a certain point in an initialization function of a scheduler in the embedded control system. The at least one event time point is an expected number of clock cycles to pass before a specific event occurs. In operation, the embedded control system is initialized, a current clock cycle counter value is retrieved at a certain point in the initialization, and either an occurrence or an absence of an occurrence of a scheduled event is recognized. A current clock cycle value is recorded upon the recognition, and a mathematic check value is produced from the clock cycle value stored at the certain point in the initialization and the clock cycle value recorded upon the recognition.Type: GrantFiled: March 18, 2014Date of Patent: January 31, 2017Assignees: STMicroelectronics International N.V., STMicroelectronics S.R.L.Inventors: Om Ranjan, Giampiero Borgonovo, Deepak Baranwal
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Publication number: 20150268133Abstract: A safety system monitors faults in an embedded control system. The embedded control system is modeled to produce one or more model check values by calculating how many clock cycles will pass between an initialization time point and at least one event time point for a specific event. The initialization time point is a certain point in an initialization function of a scheduler in the embedded control system. The at least one event time point is an expected number of clock cycles to pass before a specific event occurs. In operation, the embedded control system is initialized, a current clock cycle counter value is retrieved at a certain point in the initialization, and either an occurrence or an absence of an occurrence of a scheduled event is recognized. A current clock cycle value is recorded upon the recognition, and a mathematic check value is produced from the clock cycle value stored at the certain point in the initialization and the clock cycle value recorded upon the recognition.Type: ApplicationFiled: March 18, 2014Publication date: September 24, 2015Applicants: STMicroelectronics S.r.l., STMicroelectronics International N.V.Inventors: Om Ranjan, Giampiero Borgonovo, Deepak Baranwal