Abstract: Conventional package for integration of MEMS and electronics suffer from profiles that are undesirably high to due to the thickness of the glass. Also in conventional package manufacturing, the MEMS and electronic devices are first individualized, and the individualized MEMS and electronics are combined into a package, and thus can be costly. To address these and other disadvantages, a panel level packaging is proposed. In this proposal, plural MEMS devices are integrated with plural semiconductor devices at a panel level, and the panel is then individualized into separate packages.

Abstract: Conventional package for integration of MEMS and electronics suffer from profiles that are undesirably high to due to the thickness of the glass. Also in conventional package manufacturing, the MEMS and electronic devices are first individualized, and the individualized MEMS and electronics are combined into a package, and thus can be costly. To address these and other disadvantages, a panel level packaging is proposed. In this proposal, plural MEMS devices are integrated with plural semiconductor devices at a panel level, and the panel is then individualized into separate packages.

Abstract: In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a substrate build-up film is introduced having epoxy material and a plurality of epoxy microspheres, wherein an interior of the microspheres is not fully cured. Other embodiments are also disclosed and claimed.

Abstract: A microelectronic device mounting substrate includes a bond pad with a side wall and an upper surface. A dielectric first layer is disposed on the mounting substrate and a solder mask second layer is disposed on the dielectric first layer. A uniform recess is disposed through the solder mask second layer and the dielectric first layer that exposes the portion of the bond pad upper surface.

Abstract: In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a substrate build-up film is introduced having epoxy material and a plurality of epoxy microspheres, wherein an interior of the microspheres is not fully cured. Other embodiments are also disclosed and claimed.

Abstract: In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a substrate build-up film is introduced having epoxy material and a plurality of epoxy microspheres, wherein an interior of the microspheres is not fully cured. Other embodiments are also disclosed and claimed.

Abstract: In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a substrate build-up film is introduced having epoxy material and a plurality of epoxy microspheres, wherein an interior of the microspheres is not fully cured. Other embodiments are also disclosed and claimed.

Abstract: In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a substrate build-up film is introduced having epoxy material and a plurality of epoxy microspheres, wherein an interior of the microspheres is not fully cured. Other embodiments are also disclosed and claimed.

Abstract: A method of forming solder bumps on a substrate is disclosed. The method includes forming a plurality of contact points on the substrate. The method further includes depositing a layer of surface finish material on the plurality of contact points. Furthermore, the method includes disposing a plurality of solder balls on the layer of surface finish material. Each solder ball of the plurality of solder balls has conductive material including a solder alloy and Phosphorus. Thereafter, the method includes applying a solder reflow process to the plurality of solder balls to configure a plurality of solder bumps on the substrate layer. The concentration of the Phosphorus in the solder material is based on target performance characteristic of the substrate having the plurality of solder bumps.

Abstract: A composition includes a bismaleimide triazine (BT) compound with a nanoclay composited therewith. A mounting substrate includes polymer compound with a nanoclay composited therewith to form a core for the mounting substrate. A process includes melt blending a polymer such as BT with a nanoclay and forming a core. A process includes dissolving a monomer such as BT with a nanoclay and forming a core. A system includes a nanoclay dispersed in a polymer matrix and a microelectronic device mounted on the mounting substrate that includes the nanoclay dispersed in the polymer matrix.

Abstract: A sacrificial material applied to a thin die prior to die attach provides stability to the thin die and inhibits warpage of the thin die as heat is applied to the die and substrate during die attach. The sacrificial material may be a material that sublimates at a temperature near the reflow temperature of interconnects on the thin die. A die attach process deposits the sacrificial material on the die, attaches the die to a substrate, and applies a first temperature to reflow the interconnects. At the first temperature, the sacrificial material maintains substantially the same thickness. A second temperature is applied to sublimate the sacrificial material leaving a clean surface for the later packaging processes. Examples of the sacrificial material include polypropylene carbonate and polyethylene carbonate.

Abstract: Optical die structures and associated package substrates are generally described. In one example, an electronic device includes a package substrate having a package substrate core, a dielectric layer coupled with the package substrate core, and one or more input/output (I/O) optical fibers coupled with the package substrate core or coupled with the build-up dielectric layer, or combinations thereof, the one or more I/O optical fibers to guide I/O optical signals to and from the package substrate wherein the one or more I/O optical fibers allow both input and output optical signals to travel through the one or more I/O optical fibers.

Abstract: Optical die structures and associated package substrates are generally described. In one example, an electronic device includes a package substrate having a package substrate core, a dielectric layer coupled with the package substrate core, and one or more input/output (I/O) optical fibers coupled with the package substrate core or coupled with the build-up dielectric layer, or combinations thereof, the one or more I/O optical fibers to guide I/O optical signals to and from the package substrate wherein the one or more I/O optical fibers allow both input and output optical signals to travel through the one or more I/O optical fibers.

Abstract: A technique to remove dry film resist residues during solder bump formation. A resist assembly is formed on a metal pad on a substrate. The resist assembly includes a solder resist (SR) layer, a poly-electrolyte multi-layer (PEMU), and a dry film resist (DFR). A SR opening is formed in the resist assembly. A solder bump is formed on the SR opening. The PEMU is removed.

Abstract: A method of forming solder bumps on a substrate is disclosed. The method includes forming a plurality of contact points on the substrate. The method further includes depositing a layer of surface finish material on the plurality of contact points. Furthermore, the method includes disposing a plurality of solder balls on the layer of surface finish material. Each solder ball of the plurality of solder balls has conductive material including a solder alloy and Phosphorus. Thereafter, the method includes applying a solder reflow process to the plurality of solder balls to configure a plurality of solder bumps on the substrate layer. The concentration of the Phosphorus in the solder material is based on target performance characteristic of the substrate having the plurality of solder bumps.

Abstract: A method of enabling selective area plating on a substrate includes forming a first electrically conductive layer (310) over substantially all of the substrate, covering sections of the first electrically conductive layer with a mask (410) such that the first electrically conductive layer has a masked portion and an unmasked portion, forming a second electrically conductive layer (710, 1210), the second electrically conductive layer forming only over the unmasked portion of the first electrically conductive layer, and removing the mask and the masked portion of the first electrically conductive layer. In an embodiment, the mask covering sections of the first electrically conductive layer is a non-electrically conductive substance (1010) applied with a stamp (1020). In an embodiment, the mask is a black oxide layer.

Abstract: Disclosed is a method for preparing a printed circuit board. The method comprises forming a conductive layer on an insulated layer substrate. The method further includes partitioning the conductive layer into a first area and a second area by applying a photoresist mask. Furthermore, the method includes applying a first etching process to the conductive layer to pattern a first set of features on the first area of the conductive layer. Thereafter, the method includes applying a second etching process to the conductive layer to pattern a second set of features on the second area of the conductive layer. The second set of features on the second area of the conductive layer has a finer pitch as compared to the first set of features on the first area of the conductive layer.

Abstract: Methods for forming traces/lines and interconnects on substrates and devices and systems thereof of herein disclosed. In some embodiments, an activator layer is deposited on a surface of a substrate. Pick-up lithography using a pre-patterned lithographic stamp, ultraviolet lithography or like methods are used to selectively remove portions of the activator layer to form a pattern on the surface of the substrate. Electroless metal deposition is then applied to the surface of the substrate to form a metal pattern selectively on the remaining activator layer. Electroless plating can then be used to form traces/lines and interconnects in dimensions of less than 10 micrometers.

Abstract: A technique to remove dry film resist residues during solder bump formation. A resist assembly is formed on a metal pad on a substrate. The resist assembly includes a solder resist (SR) layer, a poly-electrolyte multi-layer (PEMU), and a dry film resist (DFR). A SR opening is formed in the resist assembly. A solder bump is formed on the SR opening. The PEMU is removed.

Abstract: A composition includes a bismaleimide triazine (BT) compound with a nanoclay composited therewith. A mounting substrate includes polymer compound with a nanoclay composited therewith to form a core for the mounting substrate. A process includes melt blending a polymer such as BT with a nanoclay and forming a core. A process includes dissolving a monomer such as BT with a nanoclay and forming a core. A system includes a nanoclay dispersed in a polymer matrix and a microelectronic device mounted on the mounting substrate that includes the nanoclay dispersed in the polymer matrix.