Abstract: Memory devices having electro-optical substrates are described herein. In one embodiment, a memory device includes a plurality of memories carried by an electro-optical substrate. The electro-optical substrate can include a circuit board and an optical routing layer on the circuit board. The memories can be (a) electrically coupled to the circuit board and (b) optically coupled to the optical routing layer. In some embodiments, the optical routing layer is a polymer waveguide.

Abstract: Memory devices having optical I/O interfaces are described herein. In one embodiment, a memory device includes a plurality of memories coupled to a substrate, each memory including one or more photon integrated circuit (PIC) chips for converting electrical signals to/from optical signals. The memory device can further include a plurality of optical fibers, wherein individual ones of the memories are optically coupled to at least one of the optical fibers. The memories can receive/transmit the optical signals over the optical fibers and can be electrically coupled to a power supply/ground via the substrate.

Abstract: Memory devices having electro-optical substrates are described herein. In one embodiment, a memory device includes a plurality of memories carried by an electro-optical substrate. The electro-optical substrate can include a circuit board and an optical routing layer on the circuit board. The memories can be (a) electrically coupled to the circuit board and (b) optically coupled to the optical routing layer. In some embodiments, the optical routing layer is a polymer waveguide.

Abstract: Memory devices having optical I/O interfaces are described herein. In one embodiment, a memory device includes a plurality of memories coupled to a substrate, each memory including one or more photon integrated (PIC) chips for converting electrical signals to/from optical signals. The memory device can further include a plurality of optical fibers, wherein individual ones of the memories are optically coupled to at least one of the optical fibers. The memories can receive/transmit the optical signals over the optical fibers and can be electrically coupled to a power supply/ground via the substrate.

Abstract: Memory devices having electro-optical substrates are described herein. In one embodiment, a memory device includes a plurality of memories carried by an electro-optical substrate. The electro-optical substrate can include a circuit board and an optical routing layer on the circuit board. The memories can be (a) electrically coupled to the circuit board and (b) optically coupled to the optical routing layer. In some embodiments, the optical routing layer is a polymer waveguide.

Abstract: Memory devices having optical I/O interfaces are described herein. In one embodiment, a memory device includes a plurality of memories coupled to a substrate, each memory including one or more photon integrated (PIC) chips for converting electrical signals to/from optical signals. The memory device can further include a plurality of optical fibers, wherein individual ones of the memories are optically coupled to at least one of the optical fibers. The memories can receive/transmit the optical signals over the optical fibers and can be electrically coupled to a power supply/ground via the substrate.

Abstract: Memory devices having electro-optical substrates are described herein. In one embodiment, a memory device includes a plurality of memories carried by an electro-optical substrate. The electro-optical substrate can include a circuit board and an optical routing layer on the circuit board. The memories can be (a) electrically coupled to the circuit board and (b) optically coupled to the optical routing layer. In some embodiments, the optical routing layer is a polymer waveguide.

Abstract: A solder on trace device includes a conductive trace on a semiconductor substrate surface. The conductive trace has a sidewall and a bonding surface. The solder on trace device also includes a passivation layer on at least one end of the conductive trace. The solder on trace device further includes a pre-solder material on the sidewall and the bonding surface of the conductive trace.

Abstract: Some implementations provide a semiconductor device that includes a substrate coupled to a die through a thermal compression bonding process. The semiconductor device also includes a trace coupled to the substrate. The trace includes a first conductive material having a first oxidation property. The trace also includes a first surface layer including a second conductive material having a second oxidation property. The second oxidation property is less susceptible to oxidation than the first oxidation property. The first and second conductive materials are configured to provide an electrical path between the die and the substrate. The first surface layer has a thickness that is 0.3 microns (?m) or less.

Abstract: Some implementations provide a substrate that includes several traces, a solder resist layer covering the several traces, and a testing pad coupled to a trace from the several traces. The testing pad is at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate. In some implementations, the several traces have a pitch that is 100 microns (nm) or less. In some implementations, the substrate is a package substrate. In some implementations, the package substrate is a package substrate on which a thermal compression flip chip is mounted during an assembly process. In some implementations, the testing pad is free of a direct connection with a bonding component of the chip when the chip is coupled to the substrate. In some implementations, the bonding component is one of a solder ball.

Abstract: Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized.

Abstract: Sonic implementations pertain to a semiconductor device that includes a packaging substrate, a trace coupled to the packaging substrate, and a solder resist layer that covers part of the trace. The trace includes a first portion having a first width, and a second portion having a second width that is wider than the first width. In some implementations, the second portion having the second width increases the area of the trace coupled to the packaging substrate to reduce the likelihood of the trace peeling from the packaging substrate. In some implementations, the solder resist layer further includes an opening such that the second portion of the trace is exposed. In some implementations, the trace further includes a third portion located between the first portion and second portion of the trace and wherein the third portion of the trace is exposed through an opening in the solder resist layer.

Abstract: Some exemplary implementations of this disclosure pertain to an integrated circuit package that includes a substrate, a first die and a second die. The substrate includes a first set of traces and a second set of traces. The first set of traces has a first pitch. The second set of traces has a second pitch. The first pitch is less than the second pitch. In some implementations, a pitch of a set of traces defines a center to center distance between two neighboring traces, or bonding pads on a substrate. The first die is coupled to the substrate by a thermal compression bonding process. In some implementations, the first die is coupled to the first set of traces of the substrate. The second die is coupled to the substrate by a reflow bonding process. In some implementations, the second die is coupled to the second set of traces of the substrate.

Abstract: A backside mold configuration (BSMC) process for manufacturing packaged integrated circuits includes applying a mold compound to a side of a packaging substrate opposite an attached die. The mold compound is deposited on a dielectric (such as photo resist). The mold compound and dielectric are patterned after coupling a die to the packaging substrate to expose a contact pad of the packaging substrate. After patterning the mold compound and dielectric, a packaging connection is coupled to contact pads through the mold compound and dielectric. The mold compound surrounding the packaging connection reduces warpage of the packaging substrate during processing. Additionally, patterning the dielectric after attaching the die improves reliability of the packaging connection.

Abstract: Some implementations provide a semiconductor device that includes a substrate coupled to a die through a thermal compression bonding process. The semiconductor device also includes a trace coupled to the substrate. The trace includes a first conductive material having a first oxidation property. The trace also includes a first surface layer including a second conductive material having a second oxidation property. The second oxidation property is less susceptible to oxidation than the first oxidation property. The first and second conductive materials are configured to provide an electrical path between the die and the substrate. The first surface layer has a thickness that is 0.3 microns (?m) or less.

Abstract: Some implementations provide a substrate that includes a first dielectric layer, a second dielectric layer, a core layer, and a composite conductive trace. The first and second dielectric layers have a first coefficient of thermal expansion (CTE). The core layer is between the first dielectric layer and the second dielectric layer. The composite conductive trace is between the first dielectric layer and the second dielectric layer. The composite conductive trace includes copper and another material. The composite conductive trace has a second CTE that is less than a third CTE for copper to more closely match the first CTE for the first and second dielectric layers.

Abstract: Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized.

Abstract: Conventional metallization processes fail at high density or small feature size patterns. For example, during patterning dry films may collapse or lift-off resulting in short circuits or open circuits in the metallization pattern. An exemplary method for metallization of integrated circuits includes forming features such as trenches, pads, and planes in a dielectric layer and depositing and selectively treating a seed layer in desired features of the dielectric layer. The treated regions of the seed layer may be used as a seed for electroless deposition of conductive material, such as copper, into the features. When the seed layer is a catalytic ink, the seed layer may be treated by curing the catalytic ink with a laser.

Abstract: A solder on trace device includes a conductive trace on a semiconductor substrate surface. The conductive trace has a sidewall and a bonding surface. The solder on trace device also includes a passivation layer on at least one end of the conductive trace. The solder on trace device further includes a pre-solder material on the sidewall and the bonding surface of the conductive trace.

Abstract: A sacrificial material applied to a thin die prior to die attach provides stability to the thin die and inhibits warpage of the thin die as heat is applied to the die and substrate during die attach. The sacrificial material may be a material that sublimates at a temperature near the reflow temperature of interconnects on the thin die. A die attach process deposits the sacrificial material on the die, attaches the die to a substrate, and applies a first temperature to reflow the interconnects. At the first temperature, the sacrificial material maintains substantially the same thickness. A second temperature is applied to sublimate the sacrificial material leaving a clean surface for the later packaging processes. Examples of the sacrificial material include polypropylene carbonate and polyethylene carbonate.