Abstract: Systems, apparatuses and methods may provide for technology that determines a plurality of transient thermal responses for a corresponding plurality of power source locations on a semiconductor die, obtains corner block list (CBL) representations associated with a plurality of candidate floorplans, and conducts an artificial intelligence (AI) based search of the CBL representations, wherein an output of the AI based search is one or more suggested floorplans having a transient thermal response that is below a thermal threshold.

Abstract: In one embodiment, a processor includes: a power switcher circuit to receive a first voltage and charge at least one charge storage device with the first voltage in a first phase and output charge in a second phase; a selection circuit coupled to the power switcher circuit to couple the output charge to a selected one of a plurality of load circuits responsive to a control signal; and a control circuit to generate the control signal based at least in part on a comparison of a feedback voltage of a rail coupled to the selected load circuit to a reference voltage. Other embodiments are described and claimed.

Abstract: A processor and method are described for performing proactive throttling of execution unit ports. For example, one embodiment of a processor core comprises: a plurality of execution unit ports within an execution stage of the processor core; a scheduler unit to schedule execution of a plurality of operations to the plurality of execution unit ports; and proactive throttling logic to limit acceleration of execution of the operations by the ports to an acceleration level which does not result in significant power supply droops.

Abstract: In one embodiment, a processor includes: a power switcher circuit to receive a first voltage and charge at least one charge storage device with the first voltage in a first phase and output charge in a second phase; a selection circuit coupled to the power switcher circuit to couple the output charge to a selected one of a plurality of load circuits responsive to a control signal; and a control circuit to generate the control signal based at least in part on a comparison of a feedback voltage of a rail coupled to the selected load circuit to a reference voltage. Other embodiments are described and claimed.

Abstract: A processor and method are described for performing proactive throttling of execution unit ports. For example, one embodiment of a processor core comprises: a plurality of execution unit ports within an execution stage of the processor core; a scheduler unit to schedule execution of a plurality of operations to the plurality of execution unit ports; and proactive throttling logic to limit acceleration of execution of the operations by the ports to an acceleration level which does not result in significant power supply droops.

Abstract: Methods, apparatuses, and systems for managing power of a processing unit are described herein. Some embodiments include determining a voltage variation of a subset of current components of a current consumed by a processing unit. Other embodiments include detecting architectural events on a processing core of the processing unit and instituting various actions to reduce an input rate of instructions to the core. Other embodiments may be described and claimed.

Abstract: In general, in one aspect, the disclosure describes a system comprising a power converter, a power delivery network, a load, and a communication link between the power converter and the load. The communication link is to implement a training sequence to dynamically adjust parameters of the power converter and set load-line slope based on implementation of the system. The load includes a training capability to generate stimuli having defined patterns and to update on the stimuli application to the power converter over the communication link. The power converter includes a controller to measure noise amplitude in a power output based on the stimuli, to adjust loop parameters to reduce the noise amplitude, and to set the load-line for the power converter based on the adjusting.

Abstract: Methods, apparatuses, and systems for managing power of a processing unit are described herein. Some embodiments include determining a voltage variation of a subset of current components of a current consumed by a processing unit. Other embodiments include detecting architectural events on a processing core of the processing unit and instituting various actions to reduce an input rate of instructions to the core. Other embodiments may be described and claimed.

Abstract: In general, in one aspect, the disclosure describes a switchable on-die decoupling cell. The switchable on-die decoupling cell includes a decoupling device and a device damping element. The device damping element can serve as a digital. The damping element may be switched off in a low power mode to preserve power. Other embodiments are disclosed herein.

Abstract: An apparatus that includes a driver circuit and an active load circuit coupled to an output of the driver circuit. The active load circuit is configured to actively adjust the slew rate of a signal outputted by the driver circuit.