Abstract: A frequency synthesizer governed by a battery saving signal having sleep and awake cycles comprises a phase locked loop and a control circuit for enhancing the restart operation of the phase locked loop at the commencement of each awake cycle of the battery saving signal. More specifically, the phase locked loop includes a phase detector for locking the frequencies generated by a reference oscillator and a voltage controlled oscillator by adjusting a signal in a storage device used for governing the voltage controlled oscillator. During the sleep and awake cycles of the battery saving signal, the oscillators and phase detector are inhibited and enabled, respectively, in their operations. In addition, the storage device maintains a desired governing signal for the voltage controlled oscillator during the sleep cycles. A problem arises as a result of the oscillators not being simultaneously effectively enabled at the commencement of an awake cycle.