Abstract: A method and apparatus for receiving data from a buffer of a non-volatile memory is described. An error correction coding (ECC) operation is initiated at a controller to correct bit errors in the data. Correction data is sent from the controller to the buffer of the non-volatile memory to correct the bit errors in the data; the correction data may correspond to a portion of the data in the buffer.

Abstract: A data storage device includes a memory and a controller. The controller is configured to identify groups of bits that match any bit pattern in a first set of bit patterns. Each of the groups of bits includes a first bit of first data, a second bit of second data, and a third bit of third data to be stored at the memory. The controller is configured, based on determining that a count of the identified groups exceeds a threshold, to change multiple bits of the first data. Changing the multiple bits of the first data reduces a number of the groups of bits that match any bit pattern in the first set of bit patterns.

Abstract: A method may be performed by a data storage device and includes writing first data to a group of storage elements. Each particular storage element of the group of storage elements is assigned to a particular state of a first set of states based on a first data value to be stored in the particular storage element. The method also includes overwriting the first data in the group of storage elements with second data. Each particular storage element of the group of storage elements is assigned to a particular state of a second set of states based on a second data value to be stored in the particular storage element. At least one state is included in the first set of states and is excluded from the second set of states.

Abstract: A data storage device includes a memory and a controller. The controller is configured to identify groups of bits that match any bit pattern in a first set of bit patterns. Each of the groups of bits includes a first bit of first data, a second bit of second data, and a third bit of third data to be stored at the memory. The controller is configured, based on determining that a count of the identified groups exceeds a threshold, to change multiple bits of the first data. Changing the multiple bits of the first data reduces a number of the groups of bits that match any bit pattern in the first set of bit patterns.

Abstract: A data storage device includes a memory and a controller. The controller is configured to identify groups of bits that match any bit pattern in a first set of bit patterns. Each of the groups of bits includes a first bit of first data, a second bit of second data, and a third bit of third data to be stored at the memory. The controller is configured, in response to determining that a count of the identified groups exceeds a threshold, to change multiple bits of the first data. Changing the multiple bits of the first data reduces a number of the groups of bits that match any bit pattern in the first set of bit patterns.

Abstract: A method may be performed by a data storage device and includes writing first data to a group of storage elements. Each particular storage element of the group of storage elements is assigned to a particular state of a first set of states based on a first data value to be stored in the particular storage element. The method also includes overwriting the first data in the group of storage elements with second data. Each particular storage element of the group of storage elements is assigned to a particular state of a second set of states based on a second data value to be stored in the particular storage element. At least one state is included in the first set of states and is excluded from the second set of states.

Abstract: A method includes receiving data from a buffer of a non-volatile memory. An error correction coding (ECC) operation is initiated to correct bit errors in the data. Correction data is sent to the buffer to correct the bit errors in the data.

Abstract: A data storage device includes a memory and a controller. The controller is configured to identify groups of bits that match any bit pattern in a first set of bit patterns. Each of the groups of bits includes a first bit of first data, a second bit of second data, and a third bit of third data to be stored at the memory. The controller is configured, in response to determining that a count of the identified groups exceeds a threshold, to change multiple bits of the first data. Changing the multiple bits of the first data reduces a number of the groups of bits that match any bit pattern in the first set of bit patterns.

Abstract: A circuit is presented for determining whether or not to invert a bus, for example a data bus that is operable having multiple widths. The circuit includes comparison circuitry that can receive both the current and next values for the bus and individually compare the current and next values of the bits on the bus to determine whether these have changed. A voting circuit receives the result of these determinations and also receives an indication of width with which the bus is being operated. The voting circuit then determines a bus inversion values based upon whether the number of bits on the data that have changed exceed a value that depends upon the indication of bus width.

Abstract: A circuit is presented for determining whether or not to invert a bus, for example a data bus that is operable having multiple widths. The circuit includes comparison circuitry that can receive both the current and next values for the bus and individually compare the current and next values of the bits on the bus to determine whether these have changed. A voting circuit receives the result of these determinations and also receives an indication of width with which the bus is being operated. The voting circuit then determines a bus inversion values based upon whether the number of bits on the data that have changed exceed a value that depends upon the indication of bus width.