Patents by Inventor Omri Viner

Omri Viner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for assigning network addresses
    Patent number: 7254625
    Abstract: An IP address assignment method including assigning a chassis serial number to a node during manufacture, generating an array of unique IP addresses composed using the chassis serial number, and assigning a unique IP address from the array to each interface associated with the node.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: August 7, 2007
    Assignee: Packetlight Networks Ltd.
    Inventors: Eran Gluska, Omri Viner, Irit Shahar, Michael Mesh, Yuval Porat, Alex Cheskis
  • Method for assigning network addresses
    Publication number: 20030051014
    Abstract: An IP address assignment method including assigning a chassis serial number to a node during manufacture, generating an array of unique IP addresses composed using the chassis serial number, and assigning a unique IP address from the array to each interface associated with the node.
    Type: Application
    Filed: September 13, 2001
    Publication date: March 13, 2003
    Inventors: Eran Gluska, Omri Viner, Irit Shahar, Michael Mesh, Yuval Porat, Alex Cheskis
  • Parallel operating CPU core and DSP module for executing sequence of vector DSP code instructions to generate decoded constellation points in QAM/TCM modem application
    Patent number: 5625828
    Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.
    Type: Grant
    Filed: July 1, 1994
    Date of Patent: April 29, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Iddo Carmon, Itael Fraenkel, Omri Viner, Ronny Cohen
  • Debug mechanism for parallel-operating DSP module and CPU core
    Patent number: 5596764
    Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.
    Type: Grant
    Filed: September 14, 1994
    Date of Patent: January 21, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Gideon Intrater, Lior Katzri, Omri Viner, Raya Levitan, Yehezkel Tzadik
  • Integrated data processing system including CPU core and parallel, independently operating DSP module
    Patent number: 5592677
    Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.
    Type: Grant
    Filed: May 19, 1994
    Date of Patent: January 7, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Amos Intrater, Andy Birenbaum, Gideon Intrater, Iddo Carmon, Ilan Shimony, Itael Fraenkel, Lev Epstein, Lior Katzri, Omri Viner, Raya Levitan, Ronny Cohen, Sidi Yomtov, Yehezkel Tzadik, Zvi Greenfeld, Israel Greiss, Oved Oz, Yachin Afek, Meir Tsadik, Moshe Doron, Alberto Sandbank
  • Integrated CPU core and parallel, independently operating DSP module and time-critical core priority scheme
    Patent number: 5590357
    Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The OP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: December 31, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Amos Intrater, Andy Birenbaum, Gideon Intrater, Iddo Carmon, Ilan Shimony, Itael Fraenkel, Lev Epstein, Lior Katzri, Omri Viner, Raya Levitan, Ronny Cohen, Sidi Yomtov, Yehezkel Tzadik, Zvi Greenfeld, Israel Greiss, Oved Oz, Yachin Afek, Meir Tsadik, Moshe Doron, Alberto Sandbank
  • DTMF detection in an integrated data processing system
    Patent number: 5487173
    Abstract: The present invention is directed to an integrated data processing system that includes a general purpose (GP) CPU core for processing data in accordance with a GP instruction set and a digital signal processor (DSP) module for processing data in accordance with command-list code. The DSP module is operable to execute the command-list code independent of and in parallel with execution of the GP instruction set by the CPU core. The system also includes a mechanism for DTMF detection.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: January 23, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Israel Greiss, Ronny Cohen, Omri Viner